2018-06-22 15:19:46 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* NXP GPMI NAND flash driver
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*
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* Copyright (C) 2018 Toradex
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* Authors:
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* Stefan Agner <stefan.agner@toradex.com>
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*/
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2018-06-22 16:06:16 +00:00
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#include <linux/mtd/mtd.h>
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#include <asm/cache.h>
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#include <nand.h>
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#include <asm/mach-imx/dma.h>
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/**
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* @gf_len: The length of Galois Field. (e.g., 13 or 14)
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* @ecc_strength: A number that describes the strength of the ECC
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* algorithm.
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mtd: gpmi: change the BCH layout setting for large oob NAND
The code change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes) and proposed a new
way to set ECC layout.
Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.
The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is
1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.
2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.
Previous code has two methods for ECC layout setting, the
legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference
between these two methods is, legacy_calc_ecc_layout set the chunk size
larger chan oob size and then set the maximum ECC strength that oob can
afford. While the calc_ecc_layout_by_info set chunk size and ECC
strength according to NAND spec. It has been proved that the first
method cannot provide safe ECC strength for some modern NAND chips, so
in current code,
1. Driver read NAND parameters first and then chose the proper ECC
layout setting method.
2. If the oob is large or NAND required data chunk larger than oob size,
chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info
3. legacy_calc_ecc_layout only used for some NAND chips does not contains
necessary information. So this is only a backup plan, it is NOT
recommended to use these NAND chips.
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-04 14:08:50 +00:00
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* @ecc_chunk0_size: The size, in bytes, of a first ECC chunk.
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* @ecc_chunkn_size: The size, in bytes, of a single ECC chunk after
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* the first chunk in the page.
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2018-06-22 16:06:16 +00:00
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* @ecc_chunk_count: The number of ECC chunks in the page,
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* @block_mark_byte_offset: The byte offset in the ECC-based page view at
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* which the underlying physical block mark appears.
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* @block_mark_bit_offset: The bit offset into the ECC-based page view at
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* which the underlying physical block mark appears.
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mtd: gpmi: change the BCH layout setting for large oob NAND
The code change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes) and proposed a new
way to set ECC layout.
Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.
The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is
1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.
2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.
Previous code has two methods for ECC layout setting, the
legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference
between these two methods is, legacy_calc_ecc_layout set the chunk size
larger chan oob size and then set the maximum ECC strength that oob can
afford. While the calc_ecc_layout_by_info set chunk size and ECC
strength according to NAND spec. It has been proved that the first
method cannot provide safe ECC strength for some modern NAND chips, so
in current code,
1. Driver read NAND parameters first and then chose the proper ECC
layout setting method.
2. If the oob is large or NAND required data chunk larger than oob size,
chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info
3. legacy_calc_ecc_layout only used for some NAND chips does not contains
necessary information. So this is only a backup plan, it is NOT
recommended to use these NAND chips.
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-04 14:08:50 +00:00
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* @ecc_for_meta: The flag to indicate if there is a dedicate ecc
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* for meta.
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2018-06-22 16:06:16 +00:00
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*/
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struct bch_geometry {
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unsigned int gf_len;
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unsigned int ecc_strength;
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mtd: gpmi: change the BCH layout setting for large oob NAND
The code change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes) and proposed a new
way to set ECC layout.
Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.
The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is
1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.
2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.
Previous code has two methods for ECC layout setting, the
legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference
between these two methods is, legacy_calc_ecc_layout set the chunk size
larger chan oob size and then set the maximum ECC strength that oob can
afford. While the calc_ecc_layout_by_info set chunk size and ECC
strength according to NAND spec. It has been proved that the first
method cannot provide safe ECC strength for some modern NAND chips, so
in current code,
1. Driver read NAND parameters first and then chose the proper ECC
layout setting method.
2. If the oob is large or NAND required data chunk larger than oob size,
chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info
3. legacy_calc_ecc_layout only used for some NAND chips does not contains
necessary information. So this is only a backup plan, it is NOT
recommended to use these NAND chips.
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-04 14:08:50 +00:00
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unsigned int ecc_chunk0_size;
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unsigned int ecc_chunkn_size;
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2018-06-22 16:06:16 +00:00
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unsigned int ecc_chunk_count;
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unsigned int block_mark_byte_offset;
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unsigned int block_mark_bit_offset;
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mtd: gpmi: change the BCH layout setting for large oob NAND
The code change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes) and proposed a new
way to set ECC layout.
Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.
The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is
1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.
2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.
Previous code has two methods for ECC layout setting, the
legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference
between these two methods is, legacy_calc_ecc_layout set the chunk size
larger chan oob size and then set the maximum ECC strength that oob can
afford. While the calc_ecc_layout_by_info set chunk size and ECC
strength according to NAND spec. It has been proved that the first
method cannot provide safe ECC strength for some modern NAND chips, so
in current code,
1. Driver read NAND parameters first and then chose the proper ECC
layout setting method.
2. If the oob is large or NAND required data chunk larger than oob size,
chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info
3. legacy_calc_ecc_layout only used for some NAND chips does not contains
necessary information. So this is only a backup plan, it is NOT
recommended to use these NAND chips.
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-04 14:08:50 +00:00
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unsigned int ecc_for_meta; /* ECC for meta data */
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2018-06-22 16:06:16 +00:00
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};
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struct mxs_nand_info {
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struct nand_chip chip;
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struct udevice *dev;
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unsigned int max_ecc_strength_supported;
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bool use_minimum_ecc;
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2020-05-04 14:08:51 +00:00
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/* legacy bch geometry flag */
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bool legacy_bch_geometry;
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2018-06-22 16:06:16 +00:00
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int cur_chip;
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uint32_t cmd_queue_len;
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uint32_t data_buf_size;
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struct bch_geometry bch_geometry;
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uint8_t *cmd_buf;
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uint8_t *data_buf;
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uint8_t *oob_buf;
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uint8_t marking_block_bad;
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uint8_t raw_oob_mode;
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struct mxs_gpmi_regs *gpmi_regs;
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struct mxs_bch_regs *bch_regs;
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/* Functions with altered behaviour */
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int (*hooked_read_oob)(struct mtd_info *mtd,
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loff_t from, struct mtd_oob_ops *ops);
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int (*hooked_write_oob)(struct mtd_info *mtd,
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loff_t to, struct mtd_oob_ops *ops);
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int (*hooked_block_markbad)(struct mtd_info *mtd,
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loff_t ofs);
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/* DMA descriptors */
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struct mxs_dma_desc **desc;
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uint32_t desc_index;
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2019-11-03 15:49:43 +00:00
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/* Hardware BCH interface and randomizer */
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u32 en_randomizer;
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u32 writesize;
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u32 oobsize;
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u32 bch_flash0layout0;
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u32 bch_flash0layout1;
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};
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struct mxs_nand_layout {
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u32 nblocks;
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u32 meta_size;
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u32 data0_size;
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u32 ecc0;
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u32 datan_size;
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u32 eccn;
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2020-05-04 14:08:58 +00:00
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u32 gf_len;
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2018-06-22 16:06:16 +00:00
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};
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int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info);
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2018-06-22 15:19:46 +00:00
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int mxs_nand_init_spl(struct nand_chip *nand);
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2018-06-22 15:19:47 +00:00
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int mxs_nand_setup_ecc(struct mtd_info *mtd);
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2019-11-03 15:49:43 +00:00
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2020-05-06 12:59:19 +00:00
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void mxs_nand_mode_fcb_62bit(struct mtd_info *mtd);
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void mxs_nand_mode_fcb_40bit(struct mtd_info *mtd);
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2019-11-03 15:49:43 +00:00
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void mxs_nand_mode_normal(struct mtd_info *mtd);
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u32 mxs_nand_mark_byte_offset(struct mtd_info *mtd);
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u32 mxs_nand_mark_bit_offset(struct mtd_info *mtd);
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void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l);
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