2019-01-21 14:25:02 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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2020-08-03 11:01:45 +00:00
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* (C) Copyright 2014 - 2020 Xilinx, Inc.
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2019-01-21 14:25:02 +00:00
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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2020-05-10 17:40:03 +00:00
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#include <env.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2019-12-19 16:45:15 +00:00
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#include <asm/sections.h>
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2019-01-21 14:25:02 +00:00
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#include <dm/uclass.h>
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#include <i2c.h>
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2020-04-08 08:51:36 +00:00
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#include <linux/sizes.h>
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2020-08-03 11:01:45 +00:00
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#include <malloc.h>
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2020-03-31 10:39:37 +00:00
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#include "board.h"
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2020-08-03 11:01:45 +00:00
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#include <dm.h>
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#include <i2c_eeprom.h>
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#include <net.h>
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2019-01-21 14:25:02 +00:00
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2020-08-03 10:59:28 +00:00
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#if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
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2019-01-21 15:29:07 +00:00
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int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
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{
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int ret = -EINVAL;
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struct udevice *dev;
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ofnode eeprom;
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eeprom = ofnode_get_chosen_node("xlnx,eeprom");
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if (!ofnode_valid(eeprom))
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return -ENODEV;
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debug("%s: Path to EEPROM %s\n", __func__,
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2020-01-27 15:49:43 +00:00
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ofnode_read_chosen_string("xlnx,eeprom"));
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2019-01-21 15:29:07 +00:00
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ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
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if (ret)
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return ret;
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ret = dm_i2c_read(dev, CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, ethaddr, 6);
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if (ret)
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debug("%s: I2C EEPROM MAC address read failed\n", __func__);
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else
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debug("%s: I2C EEPROM MAC %pM\n", __func__, ethaddr);
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return ret;
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}
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2020-08-03 10:59:28 +00:00
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#endif
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2019-10-02 14:57:36 +00:00
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2020-08-03 11:01:45 +00:00
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#define EEPROM_HEADER_MAGIC 0xdaaddeed
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#define EEPROM_HDR_MANUFACTURER_LEN 16
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#define EEPROM_HDR_NAME_LEN 16
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#define EEPROM_HDR_REV_LEN 8
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#define EEPROM_HDR_SERIAL_LEN 20
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#define EEPROM_HDR_NO_OF_MAC_ADDR 4
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#define EEPROM_HDR_ETH_ALEN ETH_ALEN
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struct xilinx_board_description {
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u32 header;
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char manufacturer[EEPROM_HDR_MANUFACTURER_LEN + 1];
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char name[EEPROM_HDR_NAME_LEN + 1];
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char revision[EEPROM_HDR_REV_LEN + 1];
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char serial[EEPROM_HDR_SERIAL_LEN + 1];
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u8 mac_addr[EEPROM_HDR_NO_OF_MAC_ADDR][EEPROM_HDR_ETH_ALEN + 1];
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};
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static struct xilinx_board_description *board_info;
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#define XILINX_I2C_DETECTION_BITS 8
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/* Variable which stores pointer to array which stores eeprom content */
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struct xilinx_legacy_format {
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char board_sn[18]; /* 0x0 */
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char unused0[14]; /* 0x12 */
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char eth_mac[6]; /* 0x20 */
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char unused1[170]; /* 0x26 */
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char board_name[11]; /* 0xd0 */
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char unused2[5]; /* 0xdc */
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char board_revision[3]; /* 0xe0 */
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char unused3[29]; /* 0xe3 */
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};
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static void xilinx_eeprom_legacy_cleanup(char *eeprom, int size)
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{
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int i;
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char byte;
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for (i = 0; i < size; i++) {
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byte = eeprom[i];
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/* Remove all ffs and spaces */
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if (byte == 0xff || byte == ' ')
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eeprom[i] = 0;
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/* Convert strings to lower case */
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if (byte >= 'A' && byte <= 'Z')
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eeprom[i] = byte + 'a' - 'A';
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}
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}
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static int xilinx_read_eeprom_legacy(struct udevice *dev, char *name,
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struct xilinx_board_description *desc)
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{
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int ret, size;
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struct xilinx_legacy_format *eeprom_content;
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bool eth_valid = false;
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size = sizeof(*eeprom_content);
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eeprom_content = calloc(1, size);
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if (!eeprom_content)
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return -ENOMEM;
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debug("%s: I2C EEPROM read pass data at %p\n", __func__,
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eeprom_content);
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ret = dm_i2c_read(dev, 0, (uchar *)eeprom_content, size);
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if (ret) {
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debug("%s: I2C EEPROM read failed\n", __func__);
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free(eeprom_content);
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return ret;
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}
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xilinx_eeprom_legacy_cleanup((char *)eeprom_content, size);
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printf("Xilinx I2C Legacy format at %s:\n", name);
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printf(" Board name:\t%s\n", eeprom_content->board_name);
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printf(" Board rev:\t%s\n", eeprom_content->board_revision);
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printf(" Board SN:\t%s\n", eeprom_content->board_sn);
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eth_valid = is_valid_ethaddr((const u8 *)eeprom_content->eth_mac);
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if (eth_valid)
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printf(" Ethernet mac:\t%pM\n", eeprom_content->eth_mac);
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/* Terminating \0 chars ensure end of string */
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strcpy(desc->name, eeprom_content->board_name);
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strcpy(desc->revision, eeprom_content->board_revision);
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strcpy(desc->serial, eeprom_content->board_sn);
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if (eth_valid)
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memcpy(desc->mac_addr[0], eeprom_content->eth_mac, ETH_ALEN);
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desc->header = EEPROM_HEADER_MAGIC;
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free(eeprom_content);
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return ret;
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}
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static bool xilinx_detect_legacy(u8 *buffer)
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{
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int i;
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char c;
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for (i = 0; i < XILINX_I2C_DETECTION_BITS; i++) {
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c = buffer[i];
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if (c < '0' || c > '9')
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return false;
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}
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return true;
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}
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static int xilinx_read_eeprom_single(char *name,
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struct xilinx_board_description *desc)
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{
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int ret;
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struct udevice *dev;
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ofnode eeprom;
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u8 buffer[XILINX_I2C_DETECTION_BITS];
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eeprom = ofnode_get_aliases_node(name);
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if (!ofnode_valid(eeprom))
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return -ENODEV;
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ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
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if (ret)
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return ret;
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ret = dm_i2c_read(dev, 0, buffer, sizeof(buffer));
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if (ret) {
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debug("%s: I2C EEPROM read failed\n", __func__);
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return ret;
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}
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debug("%s: i2c memory detected: %s\n", __func__, name);
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if (xilinx_detect_legacy(buffer))
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return xilinx_read_eeprom_legacy(dev, name, desc);
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return -ENODEV;
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}
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__maybe_unused int xilinx_read_eeprom(void)
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{
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int id, highest_id;
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char name_buf[8]; /* 8 bytes should be enough for nvmem+number */
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highest_id = dev_read_alias_highest_id("nvmem");
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/* No nvmem aliases present */
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if (highest_id < 0)
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return -EINVAL;
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board_info = calloc(1, sizeof(*board_info));
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if (!board_info)
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return -ENOMEM;
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debug("%s: Highest ID %d, board_info %p\n", __func__,
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highest_id, board_info);
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for (id = 0; id <= highest_id; id++) {
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snprintf(name_buf, sizeof(name_buf), "nvmem%d", id);
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/* Ignoring return value for supporting multiple chips */
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xilinx_read_eeprom_single(name_buf, board_info);
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}
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if (board_info->header != EEPROM_HEADER_MAGIC)
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free(board_info);
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return 0;
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}
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2019-12-19 16:45:15 +00:00
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#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
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2019-10-02 14:57:36 +00:00
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void *board_fdt_blob_setup(void)
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{
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2020-09-04 14:21:47 +00:00
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void *fdt_blob;
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2020-03-19 09:23:56 +00:00
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#if !defined(CONFIG_VERSAL_NO_DDR) && !defined(CONFIG_ZYNQMP_NO_DDR)
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fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
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2019-10-02 14:57:36 +00:00
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2019-12-19 16:45:15 +00:00
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if (fdt_magic(fdt_blob) == FDT_MAGIC)
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return fdt_blob;
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2019-10-02 14:57:36 +00:00
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2019-12-19 16:45:15 +00:00
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debug("DTB is not passed via %p\n", fdt_blob);
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2020-03-19 09:23:56 +00:00
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#endif
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2019-12-19 16:45:15 +00:00
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#ifdef CONFIG_SPL_BUILD
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/* FDT is at end of BSS unless it is in a different memory region */
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if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
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fdt_blob = (ulong *)&_image_binary_end;
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else
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fdt_blob = (ulong *)&__bss_end;
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#else
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/* FDT is at end of image */
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fdt_blob = (ulong *)&_end;
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#endif
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if (fdt_magic(fdt_blob) == FDT_MAGIC)
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return fdt_blob;
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debug("DTB is also not passed via %p\n", fdt_blob);
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return NULL;
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2019-10-02 14:57:36 +00:00
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}
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#endif
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2020-03-31 10:39:37 +00:00
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int board_late_init_xilinx(void)
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{
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2020-08-12 10:16:49 +00:00
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u32 ret = 0;
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2020-08-03 11:01:45 +00:00
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int i;
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2020-08-12 10:17:53 +00:00
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phys_size_t bootm_size = gd->ram_size;
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if (CONFIG_IS_ENABLED(ARCH_ZYNQ))
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bootm_size = min(bootm_size, (phys_size_t)(SZ_512M + SZ_256M));
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2020-03-31 10:39:37 +00:00
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2020-08-12 10:16:49 +00:00
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ret |= env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
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ret |= env_set_addr("bootm_low", (void *)gd->ram_base);
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2020-08-12 10:17:53 +00:00
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ret |= env_set_addr("bootm_size", (void *)bootm_size);
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2020-08-12 10:16:49 +00:00
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2020-08-03 11:01:45 +00:00
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if (board_info) {
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if (board_info->manufacturer)
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ret |= env_set("manufacturer",
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board_info->manufacturer);
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if (board_info->name)
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ret |= env_set("board_name", board_info->name);
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if (board_info->revision)
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ret |= env_set("board_rev", board_info->revision);
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if (board_info->serial)
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ret |= env_set("board_serial", board_info->serial);
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for (i = 0; i < EEPROM_HDR_NO_OF_MAC_ADDR; i++) {
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if (!board_info->mac_addr[i])
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continue;
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if (!CONFIG_IS_ENABLED(NET))
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continue;
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if (is_valid_ethaddr((const u8 *)board_info->mac_addr[i]))
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ret |= eth_env_set_enetaddr_by_index("eth", i,
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board_info->mac_addr[i]);
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}
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}
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2020-08-12 10:16:49 +00:00
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if (ret)
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printf("%s: Saving run time variables FAILED\n", __func__);
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2020-07-09 13:57:56 +00:00
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2020-03-31 10:39:37 +00:00
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return 0;
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}
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