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u-boot/include/configs/rk3328_common.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 07:37:51 +00:00
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
#ifndef __CONFIG_RK3328_COMMON_H
#define __CONFIG_RK3328_COMMON_H
#include "rockchip-common.h"
rockchip: add CONFIG_IRAM_BASE for all SoCs Rockchip SoCs have internal sram for bootrom data area and for sdram init program space. Introduce the base address in case we need to use it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-22 11:59:09 +00:00
#define CONFIG_IRAM_BASE 0xff090000
rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 07:37:51 +00:00
#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
rockchip: rk3328: add SPL support Add SPL support for rk3328, default with of-platdata enabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [cherry picked from https://github.com/rockchip-linux/u-boot/commit/cb2b7a1bc75ebb116b1eb9b0ae0223e84d86fc4b with minor modifications] Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-08 21:27:14 +00:00
#define CONFIG_SPL_STACK 0x00400000
rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUs Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to limit the SPL size in 0x40000(start from 0) so that we don't need to do the relocate for ATF loading. Note that there will be separate BSS, STACK and MALLOC heap, so the size 0x40000(256KB) should be enough for SPL text. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-10-18 07:54:16 +00:00
#define CONFIG_SPL_MAX_SIZE 0x40000
rockchip: rk3328: add SPL support Add SPL support for rk3328, default with of-platdata enabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [cherry picked from https://github.com/rockchip-linux/u-boot/commit/cb2b7a1bc75ebb116b1eb9b0ae0223e84d86fc4b with minor modifications] Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-06-08 21:27:14 +00:00
#define CONFIG_SPL_BSS_START_ADDR 0x2000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 07:37:51 +00:00
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
/* FAT sd card locations. */
#define CONFIG_SYS_SDRAM_BASE 0
rockchip: add sdram_common for common functions There are some functions like sdram_size_mb can be re-used for different rockchip SoCs, just put them into common file. Add board_get_usable_ram_top() for ram_top init base on SDRAM_MAX_SIZE. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Added SDRAM_MAX_SIZE definition for RK3036: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> fixup: 3036 fix for sdram_common
2017-06-23 08:11:05 +00:00
#define SDRAM_MAX_SIZE 0xff000000
rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 07:37:51 +00:00
#ifndef CONFIG_SPL_BUILD
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x01f00000\0" \
rockchip: add text_offset to kernel_addr_r on aarch64 platforms Booting a aarch64 Linux kernel requires the image to be placed text_offset bytes from a 2MB aligned address. See https://www.kernel.org/doc/Documentation/arm64/booting.txt booti_setup() takes care about this alignment and will relocate the image if not properly aligned with memmove(). This can require up to double the size of the loaded image and therefore accidentally overwrite content placed there (i.e ramdisk_addr_r) for large kernel images. By adding text_offset to the default kernel_addr_r we can prevent that from happening for kernels larger 18MB and also save a few cycles. We can assume a text_offset of 0x80000 for most cases, all others will be handled by booti_setup() anyway. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-02-19 07:02:26 +00:00
"kernel_addr_r=0x02080000\0" \
rockchip: allow loading larger kernels Recent versions of the Linux kernel with many options enabled have grown large enough to overwrite the beginning of the initrd. For example, the kernel I use on my Rock64 and RockPro64 is 34.1 MiB, while only 31.5 MiB are available between kernel_addr_r and ramdisk_addr_r. This patch moves ramdisk_addr_r up by 32 MiB on the RK3328 and RK3399, allowing for much larger kernels. Signed-off-by: Ben Wolsieffer <benwolsieffer@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-03 05:40:05 +00:00
"ramdisk_addr_r=0x06000000\0"
rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 07:37:51 +00:00
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
rockchip: utilize CONFIG_DEFAULT_FDT_FILE Currently the fdtfile environment variable is set to CONFIG_DEFAULT_DEVICE_TREE which is іnternally used as U-Boot devicetree source. The OS can use a different filename and Kconfig gives us the ability to select a default devicetree via CONFIG_DEFAULT_FDT_FILE. This also gives user configuring U-Boot via menuconfig the behaviour someone would expect. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Tested-By: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-05-25 21:45:05 +00:00
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 07:37:51 +00:00
"partitions=" PARTS_DEFAULT \
BOOTENV
#endif
configs: rk3328: add support for usb and config ehci and ohci driver Add defconfig for usb and ehci and ohci controller, config maximal number of ports of the root hub for ohci driver. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-17 10:21:45 +00:00
/* rockchip ohci host driver */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
configs: rk3328: config xhci controller Add config of max root ports and add config to enable xhci controller. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-17 10:21:47 +00:00
rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 07:37:51 +00:00
#endif
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