u-boot/arch/arm/mach-uniphier/arm32/cache-uniphier.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 */

#ifndef __CACHE_UNIPHIER_H
#define __CACHE_UNIPHIER_H

#include <linux/types.h>

void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways);
void uniphier_cache_touch_range(u32 start, u32 end, u32 ways);
void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways);
void uniphier_cache_inv_way(u32 ways);
void uniphier_cache_set_active_ways(int cpu, u32 active_ways);
void uniphier_cache_enable(void);
void uniphier_cache_disable(void);

#endif /* __CACHE_UNIPHIER_H */
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
ARM: uniphier: support prefetch and touch operations for outer cache The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as SRAM by locking ways. These functions will be used to transfer the trampoline code for SMP into the locked SRAM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2016-08-10 07:08:37 +00:00			`/*`
			`* Copyright (C) 2016 Socionext Inc.`
			`* Author: Masahiro Yamada <yamada.masahiro@socionext.com>`
			`*/`

			`#ifndef __CACHE_UNIPHIER_H`
			`#define __CACHE_UNIPHIER_H`

			`#include <linux/types.h>`

			`void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways);`
			`void uniphier_cache_touch_range(u32 start, u32 end, u32 ways);`
			`void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways);`
ARM: uniphier: add uniphier_cache_inv_way() to support way invalidation This invalidates entries in specified ways of the outer cache. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2016-08-10 07:08:47 +00:00			`void uniphier_cache_inv_way(u32 ways);`
ARM: uniphier: add uniphier_cache_set_active_ways() This outer cache allows to control active ways independently for each CPU, so this function will be useful to set up active ways for a specific CPU. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2016-08-10 07:08:48 +00:00			`void uniphier_cache_set_active_ways(int cpu, u32 active_ways);`
ARM: uniphier: export uniphier_cache_enable/disable functions The System Cache (outer cache) is used not only as L2 cache, but also as locked SRAM. The functions for turning on/off it is necessary whether the L2 cache is enabled or not. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2016-08-10 07:08:42 +00:00			`void uniphier_cache_enable(void);`
			`void uniphier_cache_disable(void);`
ARM: uniphier: support prefetch and touch operations for outer cache The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as SRAM by locking ways. These functions will be used to transfer the trampoline code for SMP into the locked SRAM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2016-08-10 07:08:37 +00:00
			`#endif /* __CACHE_UNIPHIER_H */`