2021-07-25 23:16:23 +00:00
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// SPDX-License-Identifier: (GPL-2.0+)
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/*
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* Copyright (C) 2019 George Hilliard <thirtythreeforty@gmail.com>.
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <clk/sunxi.h>
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#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
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#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
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static struct ccu_clk_gate f1c100s_gates[] = {
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[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
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[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
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[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
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[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
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[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
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[CLK_BUS_I2C0] = GATE(0x068, BIT(16)),
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[CLK_BUS_I2C1] = GATE(0x068, BIT(17)),
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[CLK_BUS_I2C2] = GATE(0x068, BIT(18)),
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[CLK_BUS_PIO] = GATE(0x068, BIT(19)),
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[CLK_BUS_UART0] = GATE(0x06c, BIT(20)),
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[CLK_BUS_UART1] = GATE(0x06c, BIT(21)),
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[CLK_BUS_UART2] = GATE(0x06c, BIT(22)),
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[CLK_USB_PHY0] = GATE(0x0cc, BIT(1)),
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};
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static struct ccu_reset f1c100s_resets[] = {
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[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
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[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
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[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
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[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
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[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
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[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
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[RST_BUS_I2C0] = RESET(0x2d0, BIT(16)),
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[RST_BUS_I2C1] = RESET(0x2d0, BIT(17)),
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[RST_BUS_I2C2] = RESET(0x2d0, BIT(18)),
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[RST_BUS_UART0] = RESET(0x2d0, BIT(20)),
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[RST_BUS_UART1] = RESET(0x2d0, BIT(21)),
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[RST_BUS_UART2] = RESET(0x2d0, BIT(22)),
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};
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static const struct ccu_desc f1c100s_ccu_desc = {
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.gates = f1c100s_gates,
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.resets = f1c100s_resets,
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2022-05-09 05:29:31 +00:00
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.num_gates = ARRAY_SIZE(f1c100s_gates),
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.num_resets = ARRAY_SIZE(f1c100s_resets),
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2021-07-25 23:16:23 +00:00
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};
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static const struct udevice_id f1c100s_clk_ids[] = {
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{ .compatible = "allwinner,suniv-f1c100s-ccu",
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.data = (ulong)&f1c100s_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_suniv_f1c100s) = {
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.name = "suniv_f1c100s_ccu",
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.id = UCLASS_CLK,
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.of_match = f1c100s_clk_ids,
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.priv_auto = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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2022-05-09 05:29:33 +00:00
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.bind = sunxi_clk_bind,
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2021-07-25 23:16:23 +00:00
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};
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