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90 lines
2 KiB
C
90 lines
2 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
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*/
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#include <linux/kernel.h>
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#include "k3-psil-priv.h"
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#define PSIL_ETHERNET(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 16, \
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}, \
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}
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/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
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static struct psil_ep am654_src_ep_map[] = {
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/* PRU_ICSSG0 */
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PSIL_ETHERNET(0x4100),
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PSIL_ETHERNET(0x4101),
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PSIL_ETHERNET(0x4102),
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PSIL_ETHERNET(0x4103),
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/* PRU_ICSSG1 */
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PSIL_ETHERNET(0x4200),
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PSIL_ETHERNET(0x4201),
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PSIL_ETHERNET(0x4202),
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PSIL_ETHERNET(0x4203),
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/* PRU_ICSSG2 */
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PSIL_ETHERNET(0x4300),
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PSIL_ETHERNET(0x4301),
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PSIL_ETHERNET(0x4302),
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PSIL_ETHERNET(0x4303),
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/* CPSW0 */
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PSIL_ETHERNET(0x7000),
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};
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/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
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static struct psil_ep am654_dst_ep_map[] = {
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/* PRU_ICSSG0 */
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PSIL_ETHERNET(0xc100),
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PSIL_ETHERNET(0xc101),
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PSIL_ETHERNET(0xc102),
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PSIL_ETHERNET(0xc103),
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PSIL_ETHERNET(0xc104),
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PSIL_ETHERNET(0xc105),
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PSIL_ETHERNET(0xc106),
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PSIL_ETHERNET(0xc107),
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/* PRU_ICSSG1 */
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PSIL_ETHERNET(0xc200),
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PSIL_ETHERNET(0xc201),
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PSIL_ETHERNET(0xc202),
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PSIL_ETHERNET(0xc203),
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PSIL_ETHERNET(0xc204),
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PSIL_ETHERNET(0xc205),
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PSIL_ETHERNET(0xc206),
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PSIL_ETHERNET(0xc207),
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/* PRU_ICSSG2 */
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PSIL_ETHERNET(0xc300),
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PSIL_ETHERNET(0xc301),
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PSIL_ETHERNET(0xc302),
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PSIL_ETHERNET(0xc303),
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PSIL_ETHERNET(0xc304),
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PSIL_ETHERNET(0xc305),
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PSIL_ETHERNET(0xc306),
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PSIL_ETHERNET(0xc307),
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/* CPSW0 */
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PSIL_ETHERNET(0xf000),
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PSIL_ETHERNET(0xf001),
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PSIL_ETHERNET(0xf002),
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PSIL_ETHERNET(0xf003),
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PSIL_ETHERNET(0xf004),
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PSIL_ETHERNET(0xf005),
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PSIL_ETHERNET(0xf006),
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PSIL_ETHERNET(0xf007),
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};
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struct psil_ep_map am654_ep_map = {
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.name = "am654",
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.src = am654_src_ep_map,
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.src_count = ARRAY_SIZE(am654_src_ep_map),
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.dst = am654_dst_ep_map,
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.dst_count = ARRAY_SIZE(am654_dst_ep_map),
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};
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