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u-boot/drivers/ddr/fsl/Kconfig

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fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-28 16:43:40 +00:00
config SYS_FSL_DDR
bool
help
Select Freescale General DDR driver, shared between most Freescale
ppc: Remove sbc8641d board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. This is also the last of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well. Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-15 01:34:26 +00:00
PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
Layerscape SoCs (such as ls2080a).
fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-28 16:43:40 +00:00
config SYS_FSL_MMDC
bool
help
Select Freescale Multi Mode DDR controller (MMDC).
nxp: Cleanup some emulator related options. - Drop the emulator CONFIG test from include/configs/ls1088ardb.h - Migrate CONFIG_SYS_FSL_DDR_EMU to a select'able option in drivers/ddr/fsl/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-15 16:03:47 +00:00
config SYS_FSL_DDR_EMU
bool
help
Specify emulator support for DDR. Some DDR features such as deskew
training are not available.
nxp: Migrate a number of DDR related symbols to Kconfig - Guard most of the options in drivers/ddr/fsl/Kconfig with SYS_FSL_DDR || SYS_FSL_MMDC. - Migrate FSL_DMA, DDR_ECC, DDR_ECC_CMD, and ECC_INIT_VIA_DDRCONTROLLER to Kconfig. - Clean up the logic for including the DDR_ECC_CMD code. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-21 17:50:18 +00:00
if SYS_FSL_DDR || SYS_FSL_MMDC
fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-28 16:43:40 +00:00
config SYS_FSL_DDR_BE
bool
help
Access DDR registers in big-endian
config SYS_FSL_DDR_LE
bool
help
Access DDR registers in little-endian
configs: fsl: move DDR specific defines to Kconfig Moves below DDR specific defines to Kconfig: CONFIG_FSL_DDR_BIST CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE CONFIG_FSL_DDR_INTERACTIVE CONFIG_FSL_DDR_SYNC_REFRESH Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-01 05:22:01 +00:00
config FSL_DDR_BIST
bool
config FSL_DDR_INTERACTIVE
bool
config FSL_DDR_SYNC_REFRESH
bool
config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
bool
Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS And we remove the entries from the README for a number of already converted items. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-01 01:08:22 +00:00
config SYS_FSL_OTHER_DDR_NUM_CTRLS
bool
fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-28 16:43:40 +00:00
menu "Freescale DDR controllers"
depends on SYS_FSL_DDR
ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:45 +00:00
config SYS_NUM_DDR_CTLRS
ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:44 +00:00
int "Maximum DDR controllers"
default 3 if ARCH_LS2080A || \
ARCH_T4240
default 2 if ARCH_B4860 || \
ARCH_BSC9132 || \
ARCH_P4080 || \
ARCH_P5040 || \
armv8: lx2160a: Add LX2160A SoC Support LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
ARCH_LX2160A || \
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-23 14:58:05 +00:00
ARCH_LX2162A
ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:44 +00:00
default 1
Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2022-02-25 16:19:53 +00:00
config CHIP_SELECTS_PER_CTRL
int "Number of chip selects per controller"
default 4
Convert CONFIG_DIMM_SLOTS_PER_CTLR to Kconfig This converts the following to Kconfig: CONFIG_DIMM_SLOTS_PER_CTLR Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-30 22:07:31 +00:00
config DIMM_SLOTS_PER_CTLR
int "Number of DIMM slots per controller"
default 1
Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS And we remove the entries from the README for a number of already converted items. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-01 01:08:22 +00:00
config SYS_FSL_DDR_MAIN_NUM_CTRLS
int "Number of controllers used as main memory"
default SYS_NUM_DDR_CTLRS
fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-28 16:43:40 +00:00
config SYS_FSL_DDR_VER
int
default 50 if SYS_FSL_DDR_VER_50
default 47 if SYS_FSL_DDR_VER_47
default 46 if SYS_FSL_DDR_VER_46
default 44 if SYS_FSL_DDR_VER_44
config SYS_FSL_DDR_VER_50
bool
config SYS_FSL_DDR_VER_47
bool
config SYS_FSL_DDR_VER_46
bool
config SYS_FSL_DDR_VER_44
bool
config SYS_FSL_DDRC_GEN1
bool
help
Enable Freescale DDR controller.
config SYS_FSL_DDRC_GEN2
bool
depends on !MPC86xx
help
Enable Freescale DDR2 controller.
config SYS_FSL_DDRC_GEN3
bool
depends on PPC
help
Enable Freescale DDR3 controller for PowerPC SoCs.
config SYS_FSL_DDRC_ARM_GEN3
bool
depends on ARM
help
Enable Freescale DDR3 controller for ARM SoCs.
config SYS_FSL_DDRC_GEN4
bool
help
Enable Freescale DDR4 controller.
config SYS_FSL_HAS_DDR4
bool
config SYS_FSL_HAS_DDR3
bool
config SYS_FSL_HAS_DDR2
bool
config SYS_FSL_HAS_DDR1
bool
choice
prompt "DDR technology"
default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
config SYS_FSL_DDR4
bool "Freescale DDR4 controller"
depends on SYS_FSL_HAS_DDR4
ddr: Migrate DDR_SPD to Kconfig Move the symbol that controls building some JEDEC SPD support functions to Kconfig. This is required on the TI keystone 2 platforms and very frequently (but not always) used on large number of Freescale/NXP platforms, so use imply there. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-21 17:50:16 +00:00
imply DDR_SPD
fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-28 16:43:40 +00:00
select SYS_FSL_DDRC_GEN4
config SYS_FSL_DDR3
bool "Freescale DDR3 controller"
depends on SYS_FSL_HAS_DDR3
ddr: Migrate DDR_SPD to Kconfig Move the symbol that controls building some JEDEC SPD support functions to Kconfig. This is required on the TI keystone 2 platforms and very frequently (but not always) used on large number of Freescale/NXP platforms, so use imply there. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-21 17:50:16 +00:00
imply DDR_SPD
fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-28 16:43:40 +00:00
select SYS_FSL_DDRC_GEN3 if PPC
select SYS_FSL_DDRC_ARM_GEN3 if ARM
config SYS_FSL_DDR2
bool "Freescale DDR2 controller"
depends on SYS_FSL_HAS_DDR2
ddr: Migrate DDR_SPD to Kconfig Move the symbol that controls building some JEDEC SPD support functions to Kconfig. This is required on the TI keystone 2 platforms and very frequently (but not always) used on large number of Freescale/NXP platforms, so use imply there. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-21 17:50:16 +00:00
imply DDR_SPD
fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-28 16:43:40 +00:00
select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
config SYS_FSL_DDR1
bool "Freescale DDR1 controller"
depends on SYS_FSL_HAS_DDR1
ddr: Migrate DDR_SPD to Kconfig Move the symbol that controls building some JEDEC SPD support functions to Kconfig. This is required on the TI keystone 2 platforms and very frequently (but not always) used on large number of Freescale/NXP platforms, so use imply there. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-21 17:50:16 +00:00
imply DDR_SPD
fsl_ddr: Move DDR config options to driver Kconfig Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-12-28 16:43:40 +00:00
select SYS_FSL_DDRC_GEN1
endchoice
endmenu
arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:41 +00:00
nxp: Migrate a number of DDR related symbols to Kconfig - Guard most of the options in drivers/ddr/fsl/Kconfig with SYS_FSL_DDR || SYS_FSL_MMDC. - Migrate FSL_DMA, DDR_ECC, DDR_ECC_CMD, and ECC_INIT_VIA_DDRCONTROLLER to Kconfig. - Clean up the logic for including the DDR_ECC_CMD code. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-21 17:50:18 +00:00
config FSL_DMA
def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
config DDR_ECC
bool "ECC DDR memory support"
config DDR_ECC_CMD
bool "Access the ECC features of the memory controller"
depends on DDR_ECC && MPC83xx
default y
config ECC_INIT_VIA_DDRCONTROLLER
bool "DDR Memory controller initializes memory."
help
Use the DDR controller to auto initialize memory. If not enabled,
the DMA controller is responsible for doing this.
Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig This converts the following to Kconfig: CONFIG_SYS_DDR_RAW_TIMING Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-15 16:03:55 +00:00
config SYS_DDR_RAW_TIMING
bool "Get DDR timing information from something other than SPD"
help
This is common with soldered DDR chips onboard without SPD. DDR raw
timing parameters are extracted from datasheet and hard-coded into
header files or board specific files.
Convert CONFIG_SYS_FSL_DDR_INTLV_256B to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_INTLV_256B Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-23 17:05:12 +00:00
config SYS_FSL_DDR_INTLV_256B
bool "Enforce 256-byte interleave"
help
DDR controller interleaving on 256-byte. This is a special
interleaving mode, handled by Dickens for Freescale layerscape SoCs
with ARM core.
nxp: Migrate a number of DDR related symbols to Kconfig - Guard most of the options in drivers/ddr/fsl/Kconfig with SYS_FSL_DDR || SYS_FSL_MMDC. - Migrate FSL_DMA, DDR_ECC, DDR_ECC_CMD, and ECC_INIT_VIA_DDRCONTROLLER to Kconfig. - Clean up the logic for including the DDR_ECC_CMD code. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-21 17:50:18 +00:00
endif
Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_BR0_PRELIM CONFIG_SYS_OR1_PRELIM CONFIG_SYS_BR1_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR2_PRELIM CONFIG_SYS_OR2_PRELIM CONFIG_SYS_BR3_PRELIM CONFIG_SYS_OR3_PRELIM CONFIG_SYS_BR4_PRELIM CONFIG_SYS_OR4_PRELIM CONFIG_SYS_BR5_PRELIM CONFIG_SYS_OR5_PRELIM CONFIG_SYS_BR6_PRELIM CONFIG_SYS_OR6_PRELIM CONFIG_SYS_BR7_PRELIM CONFIG_SYS_OR7_PRELIM This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms that can set these values do so. Add the relevant SYS_BRx_PRELIM_BOOL to platforms that had not been previously migrated. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-13 23:10:40 +00:00
menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
config SYS_BR0_PRELIM_BOOL
bool "Define Bank 0"
config SYS_BR0_PRELIM
hex "Preliminary value for BR0"
depends on SYS_BR0_PRELIM_BOOL
config SYS_OR0_PRELIM
hex "Preliminary value for OR0"
depends on SYS_BR0_PRELIM_BOOL
config SYS_BR1_PRELIM_BOOL
bool "Define Bank 1"
config SYS_BR1_PRELIM
hex "Preliminary value for BR1"
depends on SYS_BR1_PRELIM_BOOL
config SYS_OR1_PRELIM
hex "Preliminary value for OR1"
depends on SYS_BR1_PRELIM_BOOL
config SYS_BR2_PRELIM_BOOL
bool "Define Bank 2"
config SYS_BR2_PRELIM
hex "Preliminary value for BR2"
depends on SYS_BR2_PRELIM_BOOL
config SYS_OR2_PRELIM
hex "Preliminary value for OR2"
depends on SYS_BR2_PRELIM_BOOL
config SYS_BR3_PRELIM_BOOL
bool "Define Bank 3"
config SYS_BR3_PRELIM
hex "Preliminary value for BR3"
depends on SYS_BR3_PRELIM_BOOL
config SYS_OR3_PRELIM
hex "Preliminary value for OR3"
depends on SYS_BR3_PRELIM_BOOL
config SYS_BR4_PRELIM_BOOL
bool "Define Bank 4"
config SYS_BR4_PRELIM
hex "Preliminary value for BR4"
depends on SYS_BR4_PRELIM_BOOL
config SYS_OR4_PRELIM
hex "Preliminary value for OR4"
depends on SYS_BR4_PRELIM_BOOL
config SYS_BR5_PRELIM_BOOL
bool "Define Bank 5"
config SYS_BR5_PRELIM
hex "Preliminary value for BR5"
depends on SYS_BR5_PRELIM_BOOL
config SYS_OR5_PRELIM
hex "Preliminary value for OR5"
depends on SYS_BR5_PRELIM_BOOL
config SYS_BR6_PRELIM_BOOL
bool "Define Bank 6"
config SYS_BR6_PRELIM
hex "Preliminary value for BR6"
depends on SYS_BR6_PRELIM_BOOL
config SYS_OR6_PRELIM
hex "Preliminary value for OR6"
depends on SYS_BR6_PRELIM_BOOL
config SYS_BR7_PRELIM_BOOL
bool "Define Bank 7"
config SYS_BR7_PRELIM
hex "Preliminary value for BR7"
depends on SYS_BR7_PRELIM_BOOL
config SYS_OR7_PRELIM
hex "Preliminary value for OR7"
depends on SYS_BR7_PRELIM_BOOL
endmenu
Convert CONFIG_SPL_COMMON_INIT_DDR to Kconfig This converts the following to Kconfig: CONFIG_SPL_COMMON_INIT_DDR Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-21 18:44:28 +00:00
if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \
TARGET_P1020RDB_PD || TARGET_P2020RDB
config COMMON_INIT_DDR
bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)"
config SPL_COMMON_INIT_DDR
bool "Do not have a TLB entry to cover common DDR init with SPD in SPL"
config TPL_COMMON_INIT_DDR
bool "Do not have a TLB entry to cover common DDR init with SPD in TPL"
endif
arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:41 +00:00
config SYS_FSL_ERRATUM_A008378
bool
ddr: fsl: Impl. Erratum A008109 Impl. erratum as descibed in errata doc. Enable A008109 for T1040 and T1024 Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-20 16:07:34 +00:00
config SYS_FSL_ERRATUM_A008109
bool
arm: layerscape: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:41 +00:00
config SYS_FSL_ERRATUM_A008511
bool
config SYS_FSL_ERRATUM_A009663
bool
config SYS_FSL_ERRATUM_A009801
bool
config SYS_FSL_ERRATUM_A009803
bool
config SYS_FSL_ERRATUM_A009942
bool
config SYS_FSL_ERRATUM_A010165
bool
powerpc: mpc85xx: Move CONFIG_SYS_FSL_ERRATUM_* to Kconfig Use Kconfig to select errata workaround. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:43 +00:00
config SYS_FSL_ERRATUM_NMG_DDR120
bool
config SYS_FSL_ERRATUM_DDR_115
bool
config SYS_FSL_ERRATUM_DDR111_DDR134
bool
config SYS_FSL_ERRATUM_DDR_A003
bool
config SYS_FSL_ERRATUM_DDR_A003474
bool
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