2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2014-04-18 08:43:40 +00:00
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/* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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2019-12-28 17:44:58 +00:00
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#include <clock_legacy.h>
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2015-11-09 06:47:45 +00:00
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#include <console.h>
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2019-08-02 15:44:25 +00:00
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#include <env_internal.h>
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2019-12-28 17:44:45 +00:00
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#include <init.h>
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2014-04-18 08:43:40 +00:00
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#include <malloc.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <spi_flash.h>
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2020-10-31 03:38:53 +00:00
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#include <asm/global_data.h>
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2016-09-25 00:20:10 +00:00
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#include "../common/spl.h"
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2014-04-18 08:43:40 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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phys_size_t get_effective_memsize(void)
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{
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return CONFIG_SYS_L3_SIZE;
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}
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unsigned long get_board_sys_clk(void)
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{
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return CONFIG_SYS_CLK_FREQ;
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}
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio, sys_clk, ccb_clk;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
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memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
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/* Update GD pointer */
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gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
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console_init_f();
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/* initialize selected port with appropriate baud rate */
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sys_clk = get_board_sys_clk();
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plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
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ccb_clk = sys_clk * plat_ratio / 2;
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2020-12-23 02:30:19 +00:00
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ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
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2014-04-18 08:43:40 +00:00
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ccb_clk / 16 / CONFIG_BAUDRATE);
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#if defined(CONFIG_SPL_MMC_BOOT)
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puts("\nSD boot...\n");
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#elif defined(CONFIG_SPL_SPI_BOOT)
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puts("\nSPI boot...\n");
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#elif defined(CONFIG_SPL_NAND_BOOT)
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puts("\nNAND boot...\n");
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#endif
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relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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2020-06-26 06:13:33 +00:00
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struct bd_info *bd;
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2014-04-18 08:43:40 +00:00
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2020-06-26 06:13:33 +00:00
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bd = (struct bd_info *)(gd + sizeof(gd_t));
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memset(bd, 0, sizeof(struct bd_info));
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2014-04-18 08:43:40 +00:00
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gd->bd = bd;
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2017-01-23 20:31:22 +00:00
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arch_cpu_init();
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2014-04-18 08:43:40 +00:00
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get_clocks();
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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2016-05-25 16:41:48 +00:00
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gd->flags |= GD_FLG_FULL_MALLOC_INIT;
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2014-04-18 08:43:40 +00:00
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#ifdef CONFIG_SPL_NAND_BOOT
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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2019-11-19 01:02:10 +00:00
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(uchar *)SPL_ENV_ADDR);
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2014-04-18 08:43:40 +00:00
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#endif
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_initialize(bd);
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mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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2019-11-19 01:02:10 +00:00
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(uchar *)SPL_ENV_ADDR);
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2014-04-18 08:43:40 +00:00
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#endif
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#ifdef CONFIG_SPL_SPI_BOOT
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2016-09-25 00:20:10 +00:00
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fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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2019-11-19 01:02:10 +00:00
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(uchar *)SPL_ENV_ADDR);
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2014-04-18 08:43:40 +00:00
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#endif
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2019-11-19 01:02:10 +00:00
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gd->env_addr = (ulong)(SPL_ENV_ADDR);
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2017-08-03 18:21:56 +00:00
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gd->env_valid = ENV_VALID;
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2014-04-18 08:43:40 +00:00
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i2c_init_all();
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2017-04-06 18:47:05 +00:00
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dram_init();
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2014-04-18 08:43:40 +00:00
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_boot();
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#elif defined(CONFIG_SPL_SPI_BOOT)
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2016-09-25 00:20:10 +00:00
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fsl_spi_boot();
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2014-04-18 08:43:40 +00:00
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#elif defined(CONFIG_SPL_NAND_BOOT)
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nand_boot();
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#endif
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}
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