2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2015-11-04 06:55:54 +00:00
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/*
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* Freescale Layerscape MC I/O wrapper
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*
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2018-05-09 05:22:17 +00:00
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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2017-11-15 06:29:31 +00:00
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* Copyright 2017 NXP
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2015-11-04 06:55:54 +00:00
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* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
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*/
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#ifndef __FSL_DPMAC_H
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#define __FSL_DPMAC_H
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/* DPMAC Version */
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2017-11-15 06:29:31 +00:00
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#define DPMAC_VER_MAJOR 4
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2015-12-24 10:02:49 +00:00
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#define DPMAC_VER_MINOR 2
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2015-11-04 06:55:54 +00:00
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/* Command IDs */
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2017-11-15 06:29:31 +00:00
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#define DPMAC_CMDID_CLOSE 0x8001
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#define DPMAC_CMDID_OPEN 0x80c1
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#define DPMAC_CMDID_CREATE 0x90c1
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#define DPMAC_CMDID_DESTROY 0x98c1
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#define DPMAC_CMDID_GET_API_VERSION 0xa0c1
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2017-11-15 06:29:31 +00:00
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#define DPMAC_CMDID_RESET 0x0051
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2017-11-15 06:29:31 +00:00
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#define DPMAC_CMDID_SET_LINK_STATE 0x0c31
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#define DPMAC_CMDID_GET_COUNTER 0x0c41
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2015-11-04 06:55:54 +00:00
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2023-05-31 16:04:31 +00:00
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/* Macros for accessing command fields smaller than 1byte */
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#define DPMAC_MASK(field) \
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GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \
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DPMAC_##field##_SHIFT)
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#define dpmac_set_field(var, field, val) \
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((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field)))
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#define dpmac_get_field(var, field) \
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(((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT)
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#pragma pack(push, 1)
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struct dpmac_cmd_open {
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__le32 dpmac_id;
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};
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struct dpmac_cmd_create {
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__le32 mac_id;
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};
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struct dpmac_cmd_destroy {
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__le32 dpmac_id;
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};
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#define DPMAC_STATE_SIZE 1
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#define DPMAC_STATE_SHIFT 0
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#define DPMAC_STATE_VALID_SIZE 1
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#define DPMAC_STATE_VALID_SHIFT 1
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struct dpmac_cmd_set_link_state {
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__le64 options;
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__le32 rate;
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__le32 pad;
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/* only least significant bit is valid */
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u8 up;
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u8 pad0[7];
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__le64 supported;
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__le64 advertising;
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};
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struct dpmac_cmd_get_counter {
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u8 type;
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};
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struct dpmac_rsp_get_counter {
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__le64 pad;
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__le64 counter;
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};
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#pragma pack(pop)
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/* Data Path MAC API
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* Contains initialization APIs and runtime control APIs for DPMAC
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*/
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struct fsl_mc_io;
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2023-05-31 16:04:31 +00:00
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int dpmac_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpmac_id, u16 *token);
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int dpmac_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token);
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/**
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* struct dpmac_cfg - Structure representing DPMAC configuration
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* @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP,
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* the MAC IDs are continuous.
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* For example: 2 WRIOPs, 16 MACs in each:
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* MAC IDs for the 1st WRIOP: 1-16,
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* MAC IDs for the 2nd WRIOP: 17-32.
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*/
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struct dpmac_cfg {
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int mac_id;
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};
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int dpmac_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
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const struct dpmac_cfg *cfg, u32 *obj_id);
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int dpmac_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags,
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u32 object_id);
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/**
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* enum dpmac_link_type - DPMAC link type
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* @DPMAC_LINK_TYPE_NONE: No link
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* @DPMAC_LINK_TYPE_FIXED: Link is fixed type
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* @DPMAC_LINK_TYPE_PHY: Link by PHY ID
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* @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
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*/
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enum dpmac_link_type {
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DPMAC_LINK_TYPE_NONE,
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DPMAC_LINK_TYPE_FIXED,
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DPMAC_LINK_TYPE_PHY,
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DPMAC_LINK_TYPE_BACKPLANE
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};
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/**
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* enum dpmac_eth_if - DPMAC Ethrnet interface
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* @DPMAC_ETH_IF_MII: MII interface
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* @DPMAC_ETH_IF_RMII: RMII interface
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* @DPMAC_ETH_IF_SMII: SMII interface
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* @DPMAC_ETH_IF_GMII: GMII interface
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* @DPMAC_ETH_IF_RGMII: RGMII interface
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* @DPMAC_ETH_IF_SGMII: SGMII interface
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* @DPMAC_ETH_IF_QSGMII: QSGMII interface
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* @DPMAC_ETH_IF_XAUI: XAUI interface
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* @DPMAC_ETH_IF_XFI: XFI interface
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*/
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enum dpmac_eth_if {
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DPMAC_ETH_IF_MII,
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DPMAC_ETH_IF_RMII,
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DPMAC_ETH_IF_SMII,
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DPMAC_ETH_IF_GMII,
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DPMAC_ETH_IF_RGMII,
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DPMAC_ETH_IF_SGMII,
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DPMAC_ETH_IF_QSGMII,
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DPMAC_ETH_IF_XAUI,
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DPMAC_ETH_IF_XFI
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};
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/* DPMAC IRQ Index and Events */
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/* IRQ index */
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#define DPMAC_IRQ_INDEX 0
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/* IRQ event - indicates a change in link state */
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#define DPMAC_IRQ_EVENT_LINK_CFG_REQ 0x00000001
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/* irq event - Indicates that the link state changed */
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#define DPMAC_IRQ_EVENT_LINK_CHANGED 0x00000002
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/**
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* struct dpmac_attr - Structure representing DPMAC attributes
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* @id: DPMAC object ID
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* @phy_id: PHY ID
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* @link_type: link type
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* @eth_if: Ethernet interface
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* @max_rate: Maximum supported rate - in Mbps
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* @version: DPMAC version
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*/
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struct dpmac_attr {
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int id;
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int phy_id;
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enum dpmac_link_type link_type;
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enum dpmac_eth_if eth_if;
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u32 max_rate;
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};
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/* DPMAC link configuration/state options */
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/* Enable auto-negotiation */
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#define DPMAC_LINK_OPT_AUTONEG 0x0000000000000001ULL
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/* Enable half-duplex mode */
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#define DPMAC_LINK_OPT_HALF_DUPLEX 0x0000000000000002ULL
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/* Enable pause frames */
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#define DPMAC_LINK_OPT_PAUSE 0x0000000000000004ULL
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/* Enable a-symmetric pause frames */
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#define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL
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/**
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* struct dpmac_link_state - DPMAC link configuration request
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* @rate: Rate in Mbps
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* @options: Enable/Disable DPMAC link cfg features (bitmap)
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* @up: Link state
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* @state_valid: Ignore/Update the state of the link
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* @supported: Speeds capability of the phy (bitmap)
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* @advertising: Speeds that are advertised for autoneg (bitmap)
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*/
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struct dpmac_link_state {
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u32 rate;
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u64 options;
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int up;
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int state_valid;
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u64 supported;
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u64 advertising;
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};
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2023-05-31 16:04:31 +00:00
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int dpmac_set_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
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struct dpmac_link_state *link_state);
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2015-11-04 06:55:54 +00:00
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/**
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* enum dpni_counter - DPNI counter types
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* @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad.
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* @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-octet frame, good or bad.
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* @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-octet frame, good or bad.
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* @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-octet frame, good or bad.
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* @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-octet frame, good or bad.
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* @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-octet frame, good or bad.
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* @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-octet frame and larger
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* (up to max frame length specified),
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* good or bad.
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* @DPMAC_CNT_ING_FRAG: counts packet which is shorter than 64 octets received
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* with a wrong CRC
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* @DPMAC_CNT_ING_JABBER: counts packet longer than the maximum frame length
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* specified, with a bad frame check sequence.
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* @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped packet due to internal errors.
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* Occurs when a receive FIFO overflows.
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* Includes also packets truncated as a result of
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* the receive FIFO overflow.
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* @DPMAC_CNT_ING_ALIGN_ERR: counts frame with an alignment error
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* (optional used for wrong SFD)
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* @DPMAC_CNT_EGR_UNDERSIZED: counts packet transmitted that was less than 64
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* octets long with a good CRC.
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* @DPMAC_CNT_ING_OVERSIZED: counts packet longer than the maximum frame length
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* specified, with a good frame check sequence.
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* @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frame (regular and PFC).
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* @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frame transmitted
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* (regular and PFC).
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* @DPMAC_CNT_ING_BYTE: counts octet received except preamble for all valid
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* frames and valid pause frames.
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* @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frame
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* @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frame
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* @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad packet received.
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* @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frame
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* @DPMAC_CNT_ING_ERR_FRAME: counts frame received with an error
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* (except for undersized/fragment frame)
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* @DPMAC_CNT_EGR_BYTE: counts octet transmitted except preamble for all valid
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* frames and valid pause frames transmitted.
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* @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frame
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* @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frame
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* @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frame
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* @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error
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* @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including
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* pause frames.
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2023-05-23 13:47:46 +00:00
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* @DPMAC_CNT_EGR_GOOD_FRAME: counts frames transmitted without error, including
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* pause frames.
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2015-11-04 06:55:54 +00:00
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*/
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enum dpmac_counter {
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DPMAC_CNT_ING_FRAME_64,
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DPMAC_CNT_ING_FRAME_127,
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DPMAC_CNT_ING_FRAME_255,
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DPMAC_CNT_ING_FRAME_511,
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DPMAC_CNT_ING_FRAME_1023,
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DPMAC_CNT_ING_FRAME_1518,
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DPMAC_CNT_ING_FRAME_1519_MAX,
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DPMAC_CNT_ING_FRAG,
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DPMAC_CNT_ING_JABBER,
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DPMAC_CNT_ING_FRAME_DISCARD,
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DPMAC_CNT_ING_ALIGN_ERR,
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DPMAC_CNT_EGR_UNDERSIZED,
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DPMAC_CNT_ING_OVERSIZED,
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DPMAC_CNT_ING_VALID_PAUSE_FRAME,
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DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
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DPMAC_CNT_ING_BYTE,
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DPMAC_CNT_ING_MCAST_FRAME,
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DPMAC_CNT_ING_BCAST_FRAME,
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DPMAC_CNT_ING_ALL_FRAME,
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DPMAC_CNT_ING_UCAST_FRAME,
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DPMAC_CNT_ING_ERR_FRAME,
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DPMAC_CNT_EGR_BYTE,
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DPMAC_CNT_EGR_MCAST_FRAME,
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DPMAC_CNT_EGR_BCAST_FRAME,
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DPMAC_CNT_EGR_UCAST_FRAME,
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DPMAC_CNT_EGR_ERR_FRAME,
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2023-05-23 13:47:46 +00:00
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DPMAC_CNT_ING_GOOD_FRAME,
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DPMAC_CNT_EGR_GOOD_FRAME,
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2015-11-04 06:55:54 +00:00
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};
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2023-05-31 16:04:31 +00:00
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int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token,
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enum dpmac_counter type, u64 *counter);
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int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags,
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u16 *major_ver, u16 *minor_ver);
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2015-11-04 06:55:54 +00:00
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#endif /* __FSL_DPMAC_H */
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