2019-01-21 08:17:30 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_HOSTNAME "kmvect1"
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#define CONFIG_KM_BOARD_NAME "kmvect1"
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/* at end of uboot partition, before env */
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#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
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2019-01-21 08:17:32 +00:00
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2019-01-21 08:17:34 +00:00
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/* include common defines/options for all Keymile boards */
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#include "km/keymile-common.h"
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#include "km/km-powerpc.h"
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2019-01-21 08:18:23 +00:00
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#include "km/km-mpc83xx.h"
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#include "km/km-mpc8309.h"
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2019-01-21 08:17:30 +00:00
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#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
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0x0000c000 | \
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MxMR_WLFx_2X)
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/*
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* QE UEC ethernet configuration
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*/
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#define CONFIG_MV88E6352_SWITCH
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#define CONFIG_KM_MVEXTSW_ADDR 0x10
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/* ethernet port connected to simple switch 88e6122 (UEC0) */
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#define CONFIG_UEC_ETH1
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#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
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#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
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#define CONFIG_FIXED_PHY 0xFFFFFFFF
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#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
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#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
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{devnum, speed, duplex}
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#define CONFIG_SYS_FIXED_PHY_PORTS \
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CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
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#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
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#endif /* __CONFIG_H */
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