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u-boot/drivers/clk/renesas/Makefile

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clk: renesas: prepare for non R-Car clock drivers Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3. This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing recursion into the drivers/clk/reneasas directory, without bringing in the R-Car support code. The support code contains platform specific access (TMU_BASE) which is not needed on other Renesas devices such as RZ/N1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 01:36:50 +00:00
obj-$(CONFIG_CLK_RCAR) += renesas-cpg-mssr.o
clk: renesas: rcar-gen3: Factor out CPG library R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but similar enough to reuse code. Introduce a new CPG library, factor out the SD clock and RPC clock handling and hook them to the generic Gen3 CPG driver so we have an equal state. Based on Linux commit [1] and [2] by Wolfram Sang [1] 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library") [2] 6f21d145b90f ("clk: renesas: cpg-lib: Move RPC clock registration to the library") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Marek: - Add rcar_clk_* prefix to all functions - Rebase on changes to clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function - Use u32_encode_bits/GENMASK bitfield ops
2023-01-26 20:06:07 +00:00
obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o
clk: renesas: Add Gen2 clock core Add common clock code for Renesas RCar Gen2 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-08 15:38:51 +00:00
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
clk: renesas: Add R8A774A1 clock tables This sync's the clock tables with the official release from Linux 5.8-RC2 and update r8a774a1_mstp_table from Ref Manual v1.00. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-06-30 14:30:08 +00:00
obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
clk: renesas: Add R8A774B1 clock tables This sync's the RZ/G2N clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-14 17:17:35 +00:00
obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
clk: renesas: Import R8A774C0 clock tables from Linux 5.9 Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
2020-10-16 07:37:14 +00:00
obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
clk: renesas: Add R8A774E1 clock tables This sync's the RZ/G2H clock tables with mainline linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2020-10-14 17:17:36 +00:00
obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
clk: renesas: Import R8A7790 H2 clock tables Import clock tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-17 22:14:25 +00:00
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
clk: renesas: Import R8A7791/R8A7793 M2 clock tables Import clock tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-08 15:38:51 +00:00
obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
clk: renesas: Import R8A7792 V2H clock tables Import clock tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-17 22:39:10 +00:00
obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
clk: renesas: Import R8A7791/R8A7793 M2 clock tables Import clock tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-08 15:38:51 +00:00
obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o
clk: renesas: Import R8A7794 E2 clock tables Import clock tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-17 22:39:57 +00:00
obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
clk: renesas: Make clock tables Kconfig configurable Add Kconfig entries for each SoC clock table, so they can be compiled in or out at build time. This can reduce the size of the binary if desired. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-08 15:32:38 +00:00
obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960 Rename CONFIG_CLK_R8A7796 for R-Car M3-W (R8A77960) to CONFIG_CLK_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_CLK_R8A77961. Based on Linux commit 92d1ebae9abf ("clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-01-26 20:02:01 +00:00
obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support Add support for the R-Car M3-W+ (R8A77961) SoC. R-Car M3-W+ is very similar to R-Car M3-W (R8A77960), which allows for both SoCs to share a driver. Based on Linux commit 2ba738d56db4 ("clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-01-26 20:02:02 +00:00
obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o
clk: renesas: Add R8A77965 clock tables Add clock tables for R8A77965 from Linux 5.0 , except for the crit, R and Z clock, which are neither used nor supported by the U-Boot clock framework yet. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 12:36:13 +00:00
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
clk: renesas: Make clock tables Kconfig configurable Add Kconfig entries for each SoC clock table, so they can be compiled in or out at build time. This can reduce the size of the binary if desired. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-08 15:32:38 +00:00
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
clk: renesas: Add R8A77980 V3H clock tables Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-07-29 17:59:44 +00:00
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
clk: renesas: Add R8A77990 E3 clock tables Add clock tables for R8A77990 E3 SoC . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-26 08:19:03 +00:00
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
clk: renesas: Make clock tables Kconfig configurable Add Kconfig entries for each SoC clock table, so they can be compiled in or out at build time. This can reduce the size of the binary if desired. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-08 15:32:38 +00:00
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
clk: renesas: Add R8A779A0 clock tables Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot
2020-08-11 03:46:34 +00:00
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
clk: renesas: Add R8A779F0 S4 clock tables Add clock tables for R8A779F0 S4 SoC Based on Linux commit 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support for R-Car S4-8") by Yoshihiro Shimoda and sync the tables up to Linux next commit 058f4df42121 ("Add linux-next specific files for 20230228") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver]
2023-02-28 21:34:39 +00:00
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
clk: renesas: Add R8A779G0 V4H clock tables Add clock tables for R8A779G0 V4H SoC from Linux next commit 058f4df42121 ("Add linux-next specific files for 20230228") There is an adjustment to the clock tables to make them easier suitable for U-Boot, PLL2 is not treated as GEN4 PLL type PLL2_VAR, but rather a plain PLL2. This should be sufficient until PLL2_VAR is implemented in the clock core. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver Treat PLL2 as non-PLL2_VAR for now]
2023-02-28 21:37:02 +00:00
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
clk: renesas: add R906G032 driver Clock driver for the Renesas RZ/N1 SoC family. This is based on Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"), with the following additional patch series applied: https://lore.kernel.org/linux-renesas-soc/20230301215520.828455-1-ralph.siemsen@linaro.org/ Notable difference: this version avoids allocating a 'struct clk' for each clock source, as this is problematic before relocation. Instead, it uses the same approach as existing Renesas R-Car Gen2/3 clock drivers, using a temporary structure filled on-the-fly. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 01:36:51 +00:00
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver This driver provides clock and reset control for the Renesas R9A07G044L (RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts: * driver code which is applicable to all SoCs in the RZ/G2L family. * static data describing the clocks and resets which are specific to the R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter) is used to indicate that both SoCs are supported. clk_set_rate() and clk_get_rate() are implemented only for the clocks that are actually used in u-boot. The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind function is called before the SCIF (serial port) driver is probed. This is required so that we can de-assert the relevant reset signal during the serial driver probe function. This patch is based on the corresponding Linux v6.5 driver (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-10-16 09:25:29 +00:00
obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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