2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2017-01-18 21:44:55 +00:00
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/*
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* Copyright (c) 2016 Google, Inc
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*/
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#ifndef _ASM_ARCH_TIMER_H
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#define _ASM_ARCH_TIMER_H
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/* Each timer has 4 control bits in ctrl1 register.
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* Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
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* such that timer X uses bits (4 * X - 4):(4 * X - 1)
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* If the timer does not support PWM, bit 4 is reserved.
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*/
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#define AST_TMC_EN (1 << 0)
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#define AST_TMC_1MHZ (1 << 1)
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#define AST_TMC_OVFINTR (1 << 2)
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#define AST_TMC_PWM (1 << 3)
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/* Timers are counted from 1 in the datasheet. */
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#define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1))
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#define AST_TMC_RATE (1000*1000)
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#ifndef __ASSEMBLY__
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/*
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* All timers share control registers, which makes it harder to make them
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* separate devices. Since only one timer is needed at the moment, making
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* it this just one device.
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*/
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struct ast_timer_counter {
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u32 status;
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u32 reload_val;
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u32 match1;
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u32 match2;
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};
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struct ast_timer {
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struct ast_timer_counter timers1[3];
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u32 ctrl1;
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u32 ctrl2;
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#ifdef CONFIG_ASPEED_AST2500
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u32 ctrl3;
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u32 ctrl1_clr;
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#else
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u32 reserved[2];
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#endif
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struct ast_timer_counter timers2[5];
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};
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ARCH_TIMER_H */
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