mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 06:42:56 +00:00
108 lines
3 KiB
C
108 lines
3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 NXP
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*/
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#ifndef __IMX8ULP_EVK_H
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#define __IMX8ULP_EVK_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_BOOTM_LEN (SZ_64M)
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#define CONFIG_SPL_MAX_SIZE (148 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_STACK 0x22050000
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#define CONFIG_SPL_BSS_START_ADDR 0x22048000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x22040000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8000 /* 32 KB */
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#define CONFIG_MALLOC_F_ADDR 0x22040000
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#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x95000000 /* SPL_RAM needed */
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
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#endif
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#define CONFIG_SERIAL_TAG
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#define CONFIG_REMAKE_ELF
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_LATE_INIT
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/* ENET Config */
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#if defined(CONFIG_FEC_MXC)
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#define CONFIG_ETHPRIME "FEC"
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#define PHY_ANEG_TIMEOUT 20000
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_FEC_MXC_PHYADDR 1
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#define IMX_FEC_BASE 0x29950000
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#endif
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#ifdef CONFIG_DISTRO_DEFAULTS
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0)
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#include <config_distro_bootcmd.h>
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#else
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#define BOOTENV
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#endif
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
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"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"image=Image\0" \
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"console=ttyLP1,115200 earlycon\0" \
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"fdt_addr_r=0x83000000\0" \
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"boot_fit=no\0" \
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"fdtfile=imx8ulp-evk.dtb\0" \
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"initrd_addr=0x83800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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/* Link Definitions */
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#define CONFIG_LOADADDR 0x80480000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_MMCROOT "/dev/mmcblk2p2"
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_16M)
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM 0x80000000
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#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
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/* Monitor Command Prompt */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_CBSIZE 2048
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Using ULP WDOG for reset */
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#define WDOG_BASE_ADDR WDG3_RBASE
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#endif
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