Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2025-02-18 06:58:54 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/drivers/ram/rockchip/Makefile

15 lines
598 B
Makefile
Raw Normal View History

drivers: cosmetic: Convert SPDX license tags to Linux Kernel style Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-26 09:02:52 +02:00
# SPDX-License-Identifier: GPL-2.0+
rockchip: rk3368: add DRAM controller driver with DRAM initialisation This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually). At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code). Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time). The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-23 00:12:05 +02:00
#
# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
#
ram: px30: add sdram driver Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3. For TPL_BUILD, the driver implement full dram init and without DM support due to the limit of internal SRAM size. For SPL and U-Boot proper, it's a simple driver with dm for get dram_info like other SoCs. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-15 11:04:43 +08:00
obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o
rockchip: rk3368: add DRAM controller driver with DRAM initialisation This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually). At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code). Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time). The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-23 00:12:05 +02:00
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
rockchip: rk3128: add sdram driver RK3128 support up to 2GB DDR3 sdram, one channel, 32bit data width. This patch is only used for U-Boot, but not for SPL which will comes later, maybe after we merge all the common code into a common file. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-28 16:04:21 +08:00
obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
rockchip: rk3188: move sdram driver to driver/ram Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-27 16:11:31 +08:00
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
rockchip: rk322x: add sdram driver Add driver for rk322x to support sdram initialize in SPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-27 16:38:22 +08:00
obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
rockchip: rk3288: move sdram driver to driver/ram Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-27 16:11:32 +08:00
obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
ram: rk3328: use common sdram driver RK3328 has a similar controller and phy with PX30, so we can use the common driver for it and remove the duplicate codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-15 11:04:44 +08:00
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
ram: rockchip: Add initial Kconfig Right now sdram drivers in rockchip SoC are built based on the SoC configs which may not be an adequate solutions while adding common or debug driver. So, add meaningful Kconfig options start with rk3399. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-15 23:58:46 +05:30
obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
ram: rockchip: add common code for sdram driver There are some function like os_reg setting, capacity detect functions, can be used as common code for different Rockchip SoCs, add a sdram_common.c for all these functions. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-15 11:04:37 +08:00
obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
Reference in a new issue Copy permalink