2016-04-07 13:58:23 +00:00
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/*
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* dts file for Xilinx ZynqMP ZCU102 RevB
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*
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* (C) Copyright 2016, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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2017-07-20 10:38:27 +00:00
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#include "zynqmp-zcu102-revA.dts"
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2016-04-07 13:58:23 +00:00
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/ {
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model = "ZynqMP ZCU102 RevB";
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};
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&gem3 {
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phy-handle = <&phyc>;
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phyc: phy@c {
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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};
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/* Cleanup from RevA */
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/delete-node/ phy@21;
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};
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/* Different qspi 512Mbit version */
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/* Fix collision with u61 */
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&i2c0 {
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i2cswitch@75 {
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i2c@2 {
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max15303@1b { /* u8 */
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compatible = "max15303";
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reg = <0x1b>;
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};
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/delete-node/ max15303@20;
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};
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};
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};
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