2019-03-27 19:14:19 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx Versal a2197 RevA System Controller
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*
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* (C) Copyright 2019, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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2021-05-10 12:55:34 +00:00
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#include <dt-bindings/phy/phy.h>
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2019-03-27 19:14:19 +00:00
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/ {
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model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */
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2019-06-28 11:16:10 +00:00
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compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
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2019-03-27 19:14:19 +00:00
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"xlnx,zynqmp-a2197", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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2021-06-03 09:46:50 +00:00
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nvmem0 = &eeprom;
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2019-03-27 19:14:19 +00:00
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &dcc;
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usb0 = &usb0;
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usb1 = &usb1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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2019-10-14 08:35:03 +00:00
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reg = <0x0 0x0 0x0 0x80000000>;
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2019-03-27 19:14:19 +00:00
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};
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2021-05-10 12:55:34 +00:00
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si5332_1: si5332_1 { /* clk0_sgmii - u142 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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2021-10-15 12:48:20 +00:00
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clock-frequency = <125000000>;
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2021-05-10 12:55:34 +00:00
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};
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si5332_2: si5332_2 { /* clk1_usb - u142 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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2019-03-27 19:14:19 +00:00
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};
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&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
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status = "okay";
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non-removable;
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disable-wp;
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bus-width = <8>;
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2020-07-22 15:42:43 +00:00
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xlnx,mio-bank = <0>;
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2019-03-27 19:14:19 +00:00
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};
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&uart0 { /* uart0 MIO38-39 */
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status = "okay";
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};
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&uart1 { /* uart1 MIO40-41 */
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status = "okay";
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};
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&sdhci1 { /* sd1 MIO45-51 cd in place */
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status = "okay";
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no-1-8-v;
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disable-wp;
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2020-07-22 15:42:43 +00:00
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xlnx,mio-bank = <1>;
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2019-03-27 19:14:19 +00:00
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};
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2021-05-10 12:55:34 +00:00
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&psgtr {
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status = "okay";
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/* sgmii, usb3 */
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clocks = <&si5332_1>, <&si5332_2>;
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clock-names = "ref0", "ref1";
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};
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2019-03-27 19:14:19 +00:00
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&gem0 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "sgmii"; /* DTG generates this properly 1512 */
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is-internal-pcspma;
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/* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
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2019-08-08 10:44:22 +00:00
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phy0: ethernet-phy@0 {
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2019-03-27 19:14:19 +00:00
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reg = <0>;
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};
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};
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&gpio {
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status = "okay";
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gpio-line-names = "", "", "", "", "", /* 0 - 4 */
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"", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
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"DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
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"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
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"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
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"", "", "", "", "", /* 25 - 29 */
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"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
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"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
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"UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
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"SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
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"SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
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"USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
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"USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
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"USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
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"USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
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"USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
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"SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
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"SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
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"SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
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"SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
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"SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
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"VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
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"SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
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"SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
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"SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
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"SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
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"SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
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"PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
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"TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
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"PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
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"MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
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"", "", "", "", "", /* 150 - 154 */
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"", "", "", "", "", /* 155 - 159 */
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"", "", "", "", "", /* 160 - 164 */
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"", "", "", "", "", /* 165 - 169 */
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"", "", "", ""; /* 170 - 174 */
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};
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&i2c0 { /* MIO 34-35 - can't stay here */
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status = "okay";
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clock-frequency = <400000>;
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i2c-mux@74 { /* u33 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
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i2c@0 { /* PMBUS1 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* On connector J98 */
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reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x7>;
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regulator-name = "reg_vcc_fmc";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <2600000>;
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/* enable-gpio = <&gpio0 23 0x4>; optional */
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};
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reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x8>;
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};
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reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x9>;
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};
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reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0xa>;
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};
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2019-07-24 09:28:52 +00:00
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reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */
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2019-07-24 09:28:52 +00:00
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compatible = "ti,tps53681", "ti,tps53679";
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2019-07-24 09:28:52 +00:00
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reg = <0x60>;
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2019-03-27 19:14:19 +00:00
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/* vccint, vcc_io_soc */
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};
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};
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i2c@1 { /* PMBUS1_INA226 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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2019-10-14 08:27:42 +00:00
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/* FIXME check alerts coming to SC */
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2019-03-27 19:14:19 +00:00
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vcc_fmc: ina226@42 { /* u81 */
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compatible = "ti,ina226";
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reg = <0x42>;
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shunt-resistor = <5000>;
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};
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vcc_ram: ina226@43 { /* u82 */
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compatible = "ti,ina226";
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reg = <0x43>;
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shunt-resistor = <5000>;
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};
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vcc_pslp: ina226@44 { /* u84 */
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compatible = "ti,ina226";
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reg = <0x44>;
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shunt-resistor = <5000>;
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};
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vcc_psfp: ina226@45 { /* u87 */
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compatible = "ti,ina226";
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reg = <0x45>;
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shunt-resistor = <5000>;
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};
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};
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i2c@2 { /* PMBUS2 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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/* On connector J104 */
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reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0xd>;
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};
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reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0xe>;
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};
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reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0xf>;
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};
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reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x10>;
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};
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reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x11>;
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};
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reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x12>;
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};
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reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x13>;
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};
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reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x14>;
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};
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reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x15>;
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};
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reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x16>;
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};
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reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x17>;
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};
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reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x19>;
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};
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reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x1a>;
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};
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reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x1b>;
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};
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reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */
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compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
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reg = <0x1c>;
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};
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|
|
reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */
|
|
|
|
compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
|
|
|
|
reg = <0x1d>;
|
|
|
|
};
|
|
|
|
reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */
|
|
|
|
compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
|
|
|
|
reg = <0x1e>;
|
|
|
|
};
|
|
|
|
reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */
|
|
|
|
compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
|
|
|
|
reg = <0x1f>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
i2c@3 { /* PMBUS2_INA226 */
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <3>;
|
|
|
|
/* FIXME check alerts coming to SC */
|
|
|
|
vccaux: ina226@40 { /* u89 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x40>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
vccaux_fmc: ina226@41 { /* u91 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x41>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
vcco_500: ina226@42 { /* u92 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x42>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
vcco_501: ina226@43 { /* u94 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x43>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
vcco_502: ina226@44 { /* u96 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x44>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
vcco_503: ina226@45 { /* u98 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x45>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
vcc_1v8: ina226@46 { /* u100 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x46>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
vcc_3v3: ina226@47 { /* u103 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x47>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
vcc_1v2_ddr4: ina226@48 { /* u105 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x48>;
|
|
|
|
shunt-resistor = <1000>;
|
|
|
|
};
|
|
|
|
vcc1v1_lp4: ina226@49 { /* u107 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x49>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
vadj_fmc: ina226@4a { /* u110 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x4a>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
mgtyavcc: ina226@4b { /* u112 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x4b>;
|
|
|
|
shunt-resistor = <1000>;
|
|
|
|
};
|
|
|
|
mgtyavtt: ina226@4c { /* u113 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x4c>;
|
|
|
|
shunt-resistor = <1000>;
|
|
|
|
};
|
|
|
|
mgtyvccaux: ina226@4d { /* u116 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x4d>;
|
|
|
|
shunt-resistor = <5000>;
|
|
|
|
};
|
|
|
|
vcc_bat: ina226@4e { /* u12 */
|
|
|
|
compatible = "ti,ina226";
|
|
|
|
reg = <0x4e>;
|
|
|
|
shunt-resistor = <10000000>; /* 10 ohm */
|
|
|
|
};
|
|
|
|
};
|
|
|
|
i2c@4 { /* LP_I2C_SM */
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <4>;
|
|
|
|
/* connected to J212G */
|
|
|
|
/* zynqmp sm alert or samtec J212H */
|
|
|
|
};
|
|
|
|
/* 5-7 unused */
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
&i2c1 { /* i2c1 MIO 36-37 */
|
|
|
|
status = "okay";
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
|
|
|
/* Must be enabled via J242 */
|
|
|
|
eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
|
|
|
|
compatible = "atmel,24c02";
|
|
|
|
reg = <0x51>;
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c-mux@74 { /* u35 */
|
|
|
|
compatible = "nxp,pca9548";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <0x74>;
|
|
|
|
/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
|
|
|
|
dc_i2c: i2c@0 { /* DC_I2C */
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
/* Use for storing information about SC board */
|
|
|
|
eeprom: eeprom@54 { /* u34 - m24128 16kB */
|
|
|
|
compatible = "st,24c128", "atmel,24c128";
|
|
|
|
reg = <0x54>;
|
|
|
|
};
|
|
|
|
si570_ref_clk: clock-generator@5d { /* u32 */
|
|
|
|
#clock-cells = <0>;
|
|
|
|
compatible = "silabs,si570";
|
|
|
|
reg = <0x5d>; /* 570JAC000900DG */
|
|
|
|
temperature-stability = <50>;
|
2019-06-25 06:55:52 +00:00
|
|
|
factory-fout = <33333333>;
|
2019-03-27 19:14:19 +00:00
|
|
|
clock-frequency = <33333333>;
|
2019-06-25 06:55:52 +00:00
|
|
|
clock-output-names = "ref_clk";
|
2021-03-09 11:43:42 +00:00
|
|
|
silabs,skip-recall;
|
2019-03-27 19:14:19 +00:00
|
|
|
};
|
|
|
|
/* Connection via Samtec J212D */
|
|
|
|
/* Use for storing information about X-PRC card */
|
|
|
|
x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
|
|
|
|
compatible = "atmel,24c02";
|
|
|
|
reg = <0x52>;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Use for setting up certain features on X-PRC card */
|
|
|
|
x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
|
|
|
|
compatible = "nxp,pca9534";
|
|
|
|
reg = <0x22>;
|
|
|
|
gpio-controller; /* IRQ not connected */
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
|
|
|
|
"", "", "", "";
|
|
|
|
gtr_sel0 {
|
|
|
|
gpio-hog;
|
|
|
|
gpios = <0 0>;
|
|
|
|
input; /* FIXME add meaning */
|
|
|
|
line-name = "sw4_1";
|
|
|
|
};
|
|
|
|
gtr_sel1 {
|
|
|
|
gpio-hog;
|
|
|
|
gpios = <1 0>;
|
|
|
|
input; /* FIXME add meaning */
|
|
|
|
line-name = "sw4_2";
|
|
|
|
};
|
|
|
|
gtr_sel2 {
|
|
|
|
gpio-hog;
|
|
|
|
gpios = <2 0>;
|
|
|
|
input; /* FIXME add meaning */
|
|
|
|
line-name = "sw4_3";
|
|
|
|
};
|
|
|
|
gtr_sel3 {
|
|
|
|
gpio-hog;
|
|
|
|
gpios = <3 0>;
|
|
|
|
input; /* FIXME add meaning */
|
|
|
|
line-name = "sw4_4";
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
i2c@1 { /* FMCP1_IIC */
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
|
|
/* FIXME connection to Samtec J51C */
|
|
|
|
/* expected eeprom 0x50 SE cards */
|
|
|
|
};
|
|
|
|
i2c@2 { /* FMCP2_IIC */
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
/* FIXME connection to Samtec J53C */
|
|
|
|
/* expected eeprom 0x50 SE cards */
|
|
|
|
};
|
|
|
|
i2c@3 { /* DDR4_DIMM1 */
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <3>;
|
|
|
|
si570_ddr_dimm1: clock-generator@60 { /* u2 */
|
|
|
|
#clock-cells = <0>;
|
|
|
|
compatible = "silabs,si570";
|
|
|
|
reg = <0x60>; /* 570BAB000299DG */
|
|
|
|
temperature-stability = <50>;
|
2019-06-25 06:55:52 +00:00
|
|
|
factory-fout = <200000000>;
|
|
|
|
clock-frequency = <200000000>;
|
|
|
|
clock-output-names = "si570_ddrdimm1_clk";
|
2019-03-27 19:14:19 +00:00
|
|
|
};
|
|
|
|
/* 0x50 SPD? */
|
|
|
|
};
|
|
|
|
i2c@4 { /* DDR4_DIMM2 */
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <4>;
|
|
|
|
si570_ddr_dimm2: clock-generator@60 { /* u3 */
|
|
|
|
#clock-cells = <0>;
|
|
|
|
compatible = "silabs,si570";
|
|
|
|
reg = <0x60>; /* 570BAB000299DG */
|
|
|
|
temperature-stability = <50>;
|
2019-06-25 06:55:52 +00:00
|
|
|
factory-fout = <200000000>;
|
|
|
|
clock-frequency = <200000000>;
|
|
|
|
clock-output-names = "si570_ddrdimm2_clk";
|
2019-03-27 19:14:19 +00:00
|
|
|
};
|
|
|
|
/* 0x50 SPD? */
|
|
|
|
};
|
|
|
|
i2c@5 { /* LPDDR4_SI570_CLK */
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <5>;
|
|
|
|
si570_lpddr4: clock-generator@60 { /* u4 */
|
|
|
|
#clock-cells = <0>;
|
|
|
|
compatible = "silabs,si570";
|
|
|
|
reg = <0x60>; /* 570BAB000299DG */
|
|
|
|
temperature-stability = <50>;
|
2019-06-25 06:55:52 +00:00
|
|
|
factory-fout = <200000000>;
|
|
|
|
clock-frequency = <200000000>;
|
|
|
|
clock-output-names = "si570_lpddr4_clk";
|
2019-03-27 19:14:19 +00:00
|
|
|
};
|
|
|
|
};
|
|
|
|
i2c@6 { /* HSDP_SI570 */
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <6>;
|
arm64: zynqmp: Fix i2c addresses for zynqmp-p-a2197
After double checking some i2c addresses are not correct. It is visible
from i2c dump
ZynqMP> i2c bus
Bus 3: i2c@ff020000
74: i2c-mux@74, offset len 1, flags 0
Bus 5: i2c@ff020000->i2c-mux@74->i2c@0
Bus 6: i2c@ff020000->i2c-mux@74->i2c@2
Bus 7: i2c@ff020000->i2c-mux@74->i2c@1
Bus 8: i2c@ff020000->i2c-mux@74->i2c@3
Bus 4: i2c@ff030000 (active 4)
74: i2c-mux@74, offset len 1, flags 0
Bus 9: i2c@ff030000->i2c-mux@74->i2c@0
Bus 10: i2c@ff030000->i2c-mux@74->i2c@3
Bus 11: i2c@ff030000->i2c-mux@74->i2c@4
Bus 12: i2c@ff030000->i2c-mux@74->i2c@5 (active 12)
51: generic_51, offset len 1, flags 0
60: generic_60, offset len 1, flags 0
74: generic_74, offset len 1, flags 0
Bus 13: i2c@ff030000->i2c-mux@74->i2c@6 (active 13)
51: generic_51, offset len 1, flags 0
5d: generic_5d, offset len 1, flags 0
74: generic_74, offset len 1, flags 0
ZynqMP> i2c dev 4
Setting bus to 4
ZynqMP> i2c mw 74 0 18
ZynqMP> i2c probe
Valid chip addresses: 18 36 37 50 51 60 74
ZynqMP> i2c mw 74 0 20
ZynqMP> i2c probe
Valid chip addresses: 51 60 74
where it is clear that si570 (u5) is at 0x60 address and 8t49n240 (u39) is
also at address 0x60 based on log above.
i2c address 0x74 is i2c mux and 0x51 is eeprom.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/0a198e9d993411e41473d130d5a5c20b6dc83458.1646639616.git.michal.simek@xilinx.com
2022-03-07 07:53:38 +00:00
|
|
|
si570_hsdp: clock-generator@60 { /* u5 */
|
2019-03-27 19:14:19 +00:00
|
|
|
#clock-cells = <0>;
|
|
|
|
compatible = "silabs,si570";
|
arm64: zynqmp: Fix i2c addresses for zynqmp-p-a2197
After double checking some i2c addresses are not correct. It is visible
from i2c dump
ZynqMP> i2c bus
Bus 3: i2c@ff020000
74: i2c-mux@74, offset len 1, flags 0
Bus 5: i2c@ff020000->i2c-mux@74->i2c@0
Bus 6: i2c@ff020000->i2c-mux@74->i2c@2
Bus 7: i2c@ff020000->i2c-mux@74->i2c@1
Bus 8: i2c@ff020000->i2c-mux@74->i2c@3
Bus 4: i2c@ff030000 (active 4)
74: i2c-mux@74, offset len 1, flags 0
Bus 9: i2c@ff030000->i2c-mux@74->i2c@0
Bus 10: i2c@ff030000->i2c-mux@74->i2c@3
Bus 11: i2c@ff030000->i2c-mux@74->i2c@4
Bus 12: i2c@ff030000->i2c-mux@74->i2c@5 (active 12)
51: generic_51, offset len 1, flags 0
60: generic_60, offset len 1, flags 0
74: generic_74, offset len 1, flags 0
Bus 13: i2c@ff030000->i2c-mux@74->i2c@6 (active 13)
51: generic_51, offset len 1, flags 0
5d: generic_5d, offset len 1, flags 0
74: generic_74, offset len 1, flags 0
ZynqMP> i2c dev 4
Setting bus to 4
ZynqMP> i2c mw 74 0 18
ZynqMP> i2c probe
Valid chip addresses: 18 36 37 50 51 60 74
ZynqMP> i2c mw 74 0 20
ZynqMP> i2c probe
Valid chip addresses: 51 60 74
where it is clear that si570 (u5) is at 0x60 address and 8t49n240 (u39) is
also at address 0x60 based on log above.
i2c address 0x74 is i2c mux and 0x51 is eeprom.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/0a198e9d993411e41473d130d5a5c20b6dc83458.1646639616.git.michal.simek@xilinx.com
2022-03-07 07:53:38 +00:00
|
|
|
reg = <0x60>; /* 570JAC000900DG */
|
2019-03-27 19:14:19 +00:00
|
|
|
temperature-stability = <50>;
|
2019-06-25 06:55:52 +00:00
|
|
|
factory-fout = <156250000>;
|
|
|
|
clock-frequency = <156250000>;
|
|
|
|
clock-output-names = "si570_hsdp_clk";
|
2019-03-27 19:14:19 +00:00
|
|
|
};
|
|
|
|
};
|
|
|
|
i2c@7 { /* PCIE_CLK */
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <7>;
|
|
|
|
/* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
|
|
|
|
/* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */
|
|
|
|
/* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
|
arm64: zynqmp: Fix i2c addresses for zynqmp-p-a2197
After double checking some i2c addresses are not correct. It is visible
from i2c dump
ZynqMP> i2c bus
Bus 3: i2c@ff020000
74: i2c-mux@74, offset len 1, flags 0
Bus 5: i2c@ff020000->i2c-mux@74->i2c@0
Bus 6: i2c@ff020000->i2c-mux@74->i2c@2
Bus 7: i2c@ff020000->i2c-mux@74->i2c@1
Bus 8: i2c@ff020000->i2c-mux@74->i2c@3
Bus 4: i2c@ff030000 (active 4)
74: i2c-mux@74, offset len 1, flags 0
Bus 9: i2c@ff030000->i2c-mux@74->i2c@0
Bus 10: i2c@ff030000->i2c-mux@74->i2c@3
Bus 11: i2c@ff030000->i2c-mux@74->i2c@4
Bus 12: i2c@ff030000->i2c-mux@74->i2c@5 (active 12)
51: generic_51, offset len 1, flags 0
60: generic_60, offset len 1, flags 0
74: generic_74, offset len 1, flags 0
Bus 13: i2c@ff030000->i2c-mux@74->i2c@6 (active 13)
51: generic_51, offset len 1, flags 0
5d: generic_5d, offset len 1, flags 0
74: generic_74, offset len 1, flags 0
ZynqMP> i2c dev 4
Setting bus to 4
ZynqMP> i2c mw 74 0 18
ZynqMP> i2c probe
Valid chip addresses: 18 36 37 50 51 60 74
ZynqMP> i2c mw 74 0 20
ZynqMP> i2c probe
Valid chip addresses: 51 60 74
where it is clear that si570 (u5) is at 0x60 address and 8t49n240 (u39) is
also at address 0x60 based on log above.
i2c address 0x74 is i2c mux and 0x51 is eeprom.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/0a198e9d993411e41473d130d5a5c20b6dc83458.1646639616.git.michal.simek@xilinx.com
2022-03-07 07:53:38 +00:00
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clock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */
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2019-03-27 19:14:19 +00:00
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#clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
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compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
|
arm64: zynqmp: Fix i2c addresses for zynqmp-p-a2197
After double checking some i2c addresses are not correct. It is visible
from i2c dump
ZynqMP> i2c bus
Bus 3: i2c@ff020000
74: i2c-mux@74, offset len 1, flags 0
Bus 5: i2c@ff020000->i2c-mux@74->i2c@0
Bus 6: i2c@ff020000->i2c-mux@74->i2c@2
Bus 7: i2c@ff020000->i2c-mux@74->i2c@1
Bus 8: i2c@ff020000->i2c-mux@74->i2c@3
Bus 4: i2c@ff030000 (active 4)
74: i2c-mux@74, offset len 1, flags 0
Bus 9: i2c@ff030000->i2c-mux@74->i2c@0
Bus 10: i2c@ff030000->i2c-mux@74->i2c@3
Bus 11: i2c@ff030000->i2c-mux@74->i2c@4
Bus 12: i2c@ff030000->i2c-mux@74->i2c@5 (active 12)
51: generic_51, offset len 1, flags 0
60: generic_60, offset len 1, flags 0
74: generic_74, offset len 1, flags 0
Bus 13: i2c@ff030000->i2c-mux@74->i2c@6 (active 13)
51: generic_51, offset len 1, flags 0
5d: generic_5d, offset len 1, flags 0
74: generic_74, offset len 1, flags 0
ZynqMP> i2c dev 4
Setting bus to 4
ZynqMP> i2c mw 74 0 18
ZynqMP> i2c probe
Valid chip addresses: 18 36 37 50 51 60 74
ZynqMP> i2c mw 74 0 20
ZynqMP> i2c probe
Valid chip addresses: 51 60 74
where it is clear that si570 (u5) is at 0x60 address and 8t49n240 (u39) is
also at address 0x60 based on log above.
i2c address 0x74 is i2c mux and 0x51 is eeprom.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/0a198e9d993411e41473d130d5a5c20b6dc83458.1646639616.git.michal.simek@xilinx.com
2022-03-07 07:53:38 +00:00
|
|
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reg = <0x60>;
|
2019-03-27 19:14:19 +00:00
|
|
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/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
|
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|
/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
|
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};
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};
|
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};
|
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};
|
|
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|
&usb0 {
|
|
|
|
status = "okay";
|
|
|
|
xlnx,usb-polarity = <0>;
|
|
|
|
xlnx,usb-reset-mode = <0>;
|
2021-07-14 12:17:19 +00:00
|
|
|
phy-names = "usb3-phy";
|
|
|
|
phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
|
2019-03-27 19:14:19 +00:00
|
|
|
};
|
|
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|
|
|
|
|
&dwc3_0 {
|
|
|
|
status = "okay";
|
|
|
|
dr_mode = "peripheral";
|
|
|
|
snps,dis_u2_susphy_quirk;
|
|
|
|
snps,dis_u3_susphy_quirk;
|
|
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|
maximum-speed = "super-speed";
|
|
|
|
};
|
|
|
|
|
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|
|
&usb1 {
|
|
|
|
status = "okay";
|
|
|
|
xlnx,usb-polarity = <0>;
|
|
|
|
xlnx,usb-reset-mode = <0>;
|
|
|
|
};
|
|
|
|
|
|
|
|
&dwc3_1 {
|
|
|
|
/delete-property/ phy-names ;
|
|
|
|
/delete-property/ phys ;
|
|
|
|
dr_mode = "host";
|
|
|
|
maximum-speed = "high-speed";
|
|
|
|
snps,dis_u2_susphy_quirk ;
|
|
|
|
snps,dis_u3_susphy_quirk ;
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&xilinx_ams {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&ams_ps {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&ams_pl {
|
|
|
|
status = "okay";
|
|
|
|
};
|