2016-09-14 03:44:06 +00:00
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CONFIG_ARM_GIC_BASE_ADDRESS
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CONFIG_AUTO_ZRELADDR
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CONFIG_BOARDDIR
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CONFIG_DFU_ALT
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CONFIG_DFU_ALT_BOOT_EMMC
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CONFIG_DFU_ALT_BOOT_SD
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CONFIG_DFU_ALT_SYSTEM
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CONFIG_DFU_ENV_SETTINGS
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CONFIG_DM9000_BASE
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CONFIG_DM9000_BYTE_SWAPPED
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CONFIG_DM9000_DEBUG
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CONFIG_DM9000_NO_SROM
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CONFIG_DM9000_USE_16BIT
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CONFIG_DW_WDT_CLOCK_KHZ
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CONFIG_ENV_FLAGS_LIST_STATIC
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CONFIG_ENV_IS_EMBEDDED
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CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS
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CONFIG_ENV_SETTINGS_NAND_V1
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CONFIG_ENV_SETTINGS_NAND_V2
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CONFIG_ENV_SETTINGS_V1
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CONFIG_ENV_SETTINGS_V2
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CONFIG_ENV_SROM_BANK
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CONFIG_ENV_TOTAL_SIZE
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CONFIG_ET1100_BASE
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CONFIG_ETHBASE
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CONFIG_EXTRA_ENV_SETTINGS
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CONFIG_FB_ADDR
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CONFIG_FDTADDR
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CONFIG_FDTFILE
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CONFIG_FEC_ENET_DEV
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CONFIG_FEC_FIXED_SPEED
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CONFIG_FEC_MXC_PHYADDR
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CONFIG_FLASH_BR_PRELIM
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CONFIG_FLASH_OR_PRELIM
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CONFIG_FLASH_SECTOR_SIZE
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CONFIG_FLASH_SHOW_PROGRESS
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CONFIG_FLASH_SPANSION_S29WS_N
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CONFIG_FLASH_VERIFY
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CONFIG_FM_PLAT_CLK_DIV
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CONFIG_FSL_CADMUS
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CONFIG_FSL_CPLD
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CONFIG_FSL_DEVICE_DISABLE
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CONFIG_FSL_ESDHC_PIN_MUX
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CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
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CONFIG_FSL_IIM
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CONFIG_FSL_ISBC_KEY_EXT
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CONFIG_FSL_LBC
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CONFIG_FSL_PMIC_BITLEN
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CONFIG_FSL_PMIC_BUS
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CONFIG_FSL_PMIC_CLK
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CONFIG_FSL_PMIC_CS
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CONFIG_FSL_PMIC_MODE
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CONFIG_FSL_SDHC_V2_3
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CONFIG_FSL_SERDES
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CONFIG_FSL_SERDES1
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CONFIG_FSL_SERDES2
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CONFIG_FTMAC100_BASE
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CONFIG_FTRTC010_EXTCLK
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CONFIG_FTRTC010_PCLK
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CONFIG_GATEWAYIP
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CONFIG_GMII
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CONFIG_G_DNL_THOR_PRODUCT_NUM
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CONFIG_G_DNL_THOR_VENDOR_NUM
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CONFIG_G_DNL_UMS_PRODUCT_NUM
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CONFIG_G_DNL_UMS_VENDOR_NUM
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CONFIG_HDMI_ENCODER_I2C_ADDR
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CONFIG_HIDE_LOGO_VERSION
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CONFIG_HIKEY_GPIO
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CONFIG_HOSTNAME
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CONFIG_HPS_ALTERAGRP_DBGATCLK
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CONFIG_HPS_ALTERAGRP_MAINCLK
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CONFIG_HPS_ALTERAGRP_MPUCLK
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CONFIG_HPS_CLK_CAN0_HZ
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CONFIG_HPS_CLK_CAN1_HZ
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CONFIG_HPS_CLK_EMAC0_HZ
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CONFIG_HPS_CLK_EMAC1_HZ
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CONFIG_HPS_CLK_F2S_PER_REF_HZ
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CONFIG_HPS_CLK_F2S_SDR_REF_HZ
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CONFIG_HPS_CLK_GPIODB_HZ
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CONFIG_HPS_CLK_L4_MP_HZ
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CONFIG_HPS_CLK_L4_SP_HZ
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CONFIG_HPS_CLK_MAINVCO_HZ
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CONFIG_HPS_CLK_NAND_HZ
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CONFIG_HPS_CLK_OSC1_HZ
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CONFIG_HPS_CLK_OSC2_HZ
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CONFIG_HPS_CLK_PERVCO_HZ
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CONFIG_HPS_CLK_QSPI_HZ
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CONFIG_HPS_CLK_SDMMC_HZ
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CONFIG_HPS_CLK_SDRVCO_HZ
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CONFIG_HPS_CLK_SPIM_HZ
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CONFIG_HPS_CLK_USBCLK_HZ
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CONFIG_HPS_DBCTRL_STAYOSC1
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CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
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CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH
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CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH
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CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
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CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT
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CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT
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CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK
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CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK
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CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP
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CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP
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CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK
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CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK
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CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT
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CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT
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CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT
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CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK
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CONFIG_HPS_MAINPLLGRP_VCO_DENOM
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CONFIG_HPS_MAINPLLGRP_VCO_NUMER
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CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK
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CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK
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CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK
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CONFIG_HPS_PERPLLGRP_DIV_USBCLK
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CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT
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CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT
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CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK
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CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT
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CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT
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CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT
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CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT
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CONFIG_HPS_PERPLLGRP_SRC_NAND
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CONFIG_HPS_PERPLLGRP_SRC_QSPI
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CONFIG_HPS_PERPLLGRP_SRC_SDMMC
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CONFIG_HPS_PERPLLGRP_VCO_DENOM
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CONFIG_HPS_PERPLLGRP_VCO_NUMER
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CONFIG_HPS_PERPLLGRP_VCO_PSRC
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CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT
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CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE
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CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT
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CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE
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CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT
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CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE
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CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT
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CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE
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CONFIG_HPS_SDRPLLGRP_VCO_DENOM
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CONFIG_HPS_SDRPLLGRP_VCO_NUMER
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CONFIG_HPS_SDRPLLGRP_VCO_SSRC
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CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR
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CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP
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CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH
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CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT
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CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH
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CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS
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CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS
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CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS
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CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS
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CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH
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CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH
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CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN
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CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ
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CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT
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CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT
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CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC
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CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE
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CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST
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CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED
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CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED
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CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED
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CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK
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CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES
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CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES
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CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0
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CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32
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CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0
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CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4
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CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36
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CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY
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CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0
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CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32
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CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64
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CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0
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CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32
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CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0
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CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14
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CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46
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CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0
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CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN
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CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP
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CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
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CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
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CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
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CONFIG_HSMMC2_8BIT
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CONFIG_HWCONFIG
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CONFIG_HW_ENV_SETTINGS
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CONFIG_I2C_ENV_EEPROM_BUS
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CONFIG_I2C_MULTI_BUS
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CONFIG_I2C_MVTWSI
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CONFIG_I2C_MVTWSI_BASE
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CONFIG_I2C_MVTWSI_BASE0
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CONFIG_I2C_MVTWSI_BASE1
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CONFIG_I2C_RTC_ADDR
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CONFIG_ICS307_REFCLK_HZ
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CONFIG_IMX
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CONFIG_IMX6_PWM_PER_CLK
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CONFIG_IMX_HDMI
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CONFIG_IMX_VIDEO_SKIP
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CONFIG_INTERRUPTS
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CONFIG_IODELAY_RECALIBRATION
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CONFIG_IOMUX_LPSR
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CONFIG_IOMUX_SHARE_CONF_REG
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CONFIG_IO_TRACE
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CONFIG_IPADDR
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CONFIG_IRAM_BASE
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CONFIG_IRAM_END
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CONFIG_IRAM_SIZE
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CONFIG_IRAM_TOP
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CONFIG_KM_DEF_ARCH
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CONFIG_KM_DEF_BOOT_ARGS_CPU
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CONFIG_KM_DEF_ENV
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CONFIG_KM_DEF_ENV_BOOTARGS
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CONFIG_KM_DEF_ENV_BOOTPARAMS
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CONFIG_KM_DEF_ENV_BOOTTARGETS
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CONFIG_KM_DEF_ENV_CONSTANTS
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CONFIG_KM_DEF_ENV_CPU
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CONFIG_KM_DEF_ENV_FLASH_BOOT
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CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
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CONFIG_KM_ECC_MODE
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CONFIG_KM_NEW_ENV
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CONFIG_KM_ROOTFSSIZE
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CONFIG_KM_UBI_LINUX_MTD
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CONFIG_KM_UBI_PARTITION_NAME_APP
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CONFIG_KM_UBI_PARTITION_NAME_BOOT
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CONFIG_KM_UBI_PART_BOOT_OPTS
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CONFIG_KM_UIMAGE_NAME
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CONFIG_KM_UPDATE_UBOOT
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CONFIG_KSNET_CPSW_NUM_PORTS
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CONFIG_KSNET_MAC_ID_BASE
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CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
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CONFIG_KSNET_NETCP_BASE
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CONFIG_KSNET_NETCP_V1_0
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CONFIG_KSNET_NETCP_V1_5
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CONFIG_KSNET_SERDES_LANES_PER_SGMII
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CONFIG_KSNET_SERDES_SGMII2_BASE
|
|
|
|
|
CONFIG_KSNET_SERDES_SGMII_BASE
|
|
|
|
|
CONFIG_L1_INIT_RAM
|
|
|
|
|
CONFIG_L2_CACHE
|
|
|
|
|
CONFIG_LCD_ALIGNMENT
|
|
|
|
|
CONFIG_LCD_MENU
|
|
|
|
|
CONFIG_LD9040
|
|
|
|
|
CONFIG_LEGACY_BOOTCMD_ENV
|
|
|
|
|
CONFIG_LOADS_ECHO
|
|
|
|
|
CONFIG_LOWPOWER_ADDR
|
|
|
|
|
CONFIG_LOWPOWER_FLAG
|
|
|
|
|
CONFIG_LPC32XX_HSUART
|
|
|
|
|
CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY
|
|
|
|
|
CONFIG_LPC32XX_NAND_MLC_NAND_TA
|
|
|
|
|
CONFIG_LPC32XX_NAND_MLC_RD_HIGH
|
|
|
|
|
CONFIG_LPC32XX_NAND_MLC_RD_LOW
|
|
|
|
|
CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY
|
|
|
|
|
CONFIG_LPC32XX_NAND_MLC_WR_HIGH
|
|
|
|
|
CONFIG_LPC32XX_NAND_MLC_WR_LOW
|
|
|
|
|
CONFIG_LPC32XX_NAND_SLC_RDR_CLKS
|
|
|
|
|
CONFIG_LPC32XX_NAND_SLC_RHOLD
|
|
|
|
|
CONFIG_LPC32XX_NAND_SLC_RSETUP
|
|
|
|
|
CONFIG_LPC32XX_NAND_SLC_RWIDTH
|
|
|
|
|
CONFIG_LPC32XX_NAND_SLC_WDR_CLKS
|
|
|
|
|
CONFIG_LPC32XX_NAND_SLC_WHOLD
|
|
|
|
|
CONFIG_LPC32XX_NAND_SLC_WSETUP
|
|
|
|
|
CONFIG_LPC32XX_NAND_SLC_WWIDTH
|
|
|
|
|
CONFIG_LS102XA_STREAM_ID
|
|
|
|
|
CONFIG_MACB_SEARCH_PHY
|
|
|
|
|
CONFIG_MALLOC_F_ADDR
|
|
|
|
|
CONFIG_MALTA
|
|
|
|
|
CONFIG_MAX_DSP_CPUS
|
|
|
|
|
CONFIG_MAX_MEM_MAPPED
|
|
|
|
|
CONFIG_MAX_RAM_BANK_SIZE
|
|
|
|
|
CONFIG_MEMSIZE_IN_BYTES
|
|
|
|
|
CONFIG_MEM_INIT_VALUE
|
|
|
|
|
CONFIG_MFG_ENV_SETTINGS
|
|
|
|
|
CONFIG_MII_DEFAULT_TSEC
|
|
|
|
|
CONFIG_MISC_COMMON
|
|
|
|
|
CONFIG_MIU_2BIT_21_7_INTERLEAVED
|
|
|
|
|
CONFIG_MIU_2BIT_INTERLEAVED
|
|
|
|
|
CONFIG_MMC_DEFAULT_DEV
|
|
|
|
|
CONFIG_MMC_SUNXI_SLOT
|
|
|
|
|
CONFIG_MONITOR_IS_IN_RAM
|
|
|
|
|
CONFIG_MPC85XX_FEC
|
|
|
|
|
CONFIG_MPC85XX_FEC_NAME
|
|
|
|
|
CONFIG_MTD_NAND_VERIFY_WRITE
|
|
|
|
|
CONFIG_MTD_PARTITION
|
|
|
|
|
CONFIG_MVGBE_PORTS
|
|
|
|
|
CONFIG_MVS
|
|
|
|
|
CONFIG_MX27
|
|
|
|
|
CONFIG_MX27_CLK32
|
|
|
|
|
CONFIG_MXC_GPT_HCLK
|
|
|
|
|
CONFIG_MXC_NAND_HWECC
|
|
|
|
|
CONFIG_MXC_NAND_IP_REGS_BASE
|
|
|
|
|
CONFIG_MXC_NAND_REGS_BASE
|
|
|
|
|
CONFIG_MXC_UART_BASE
|
|
|
|
|
CONFIG_MXC_USB_FLAGS
|
|
|
|
|
CONFIG_MXC_USB_PORT
|
|
|
|
|
CONFIG_MXC_USB_PORTSC
|
|
|
|
|
CONFIG_MXS
|
|
|
|
|
CONFIG_MXS_OCOTP
|
|
|
|
|
CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
|
|
|
|
|
CONFIG_NAND_CS_INIT
|
|
|
|
|
CONFIG_NAND_ECC_BCH
|
|
|
|
|
CONFIG_NAND_KIRKWOOD
|
|
|
|
|
CONFIG_NAND_KMETER1
|
|
|
|
|
CONFIG_NAND_OMAP_GPMC_WSCFG
|
|
|
|
|
CONFIG_NAND_SECBOOT
|
|
|
|
|
CONFIG_NAND_SPL
|
|
|
|
|
CONFIG_NETDEV
|
|
|
|
|
CONFIG_NETMASK
|
|
|
|
|
CONFIG_NEVER_ASSERT_ODT_TO_CPU
|
|
|
|
|
CONFIG_NOBQFMAN
|
|
|
|
|
CONFIG_NORBOOT
|
|
|
|
|
CONFIG_NS16550_MIN_FUNCTIONS
|
|
|
|
|
CONFIG_NUM_DSP_CPUS
|
|
|
|
|
CONFIG_ODROID_REV_AIN
|
|
|
|
|
CONFIG_OTHBOOTARGS
|
|
|
|
|
CONFIG_OVERWRITE_ETHADDR_ONCE
|
|
|
|
|
CONFIG_PCA953X
|
|
|
|
|
CONFIG_PCIE_IMX_PERST_GPIO
|
|
|
|
|
CONFIG_PCIE_IMX_POWER_GPIO
|
|
|
|
|
CONFIG_PEN_ADDR_BIG_ENDIAN
|
|
|
|
|
CONFIG_PHY_BASE_ADR
|
|
|
|
|
CONFIG_PHY_ET1011C_TX_CLK_FIX
|
|
|
|
|
CONFIG_PHY_ID
|
|
|
|
|
CONFIG_PHY_INTERFACE_MODE
|
|
|
|
|
CONFIG_PHY_IRAM_BASE
|
|
|
|
|
CONFIG_PL011_CLOCK
|
|
|
|
|
CONFIG_PL01x_PORTS
|
|
|
|
|
CONFIG_PM
|
|
|
|
|
CONFIG_PME_PLAT_CLK_DIV
|
|
|
|
|
CONFIG_POST
|
|
|
|
|
CONFIG_POSTBOOTMENU
|
|
|
|
|
CONFIG_POST_EXTERNAL_WORD_FUNCS
|
|
|
|
|
CONFIG_POST_SKIP_ENV_FLAGS
|
|
|
|
|
CONFIG_POWER_FSL
|
|
|
|
|
CONFIG_POWER_FSL_MC13892
|
|
|
|
|
CONFIG_POWER_HI6553
|
|
|
|
|
CONFIG_POWER_LTC3676
|
|
|
|
|
CONFIG_POWER_LTC3676_I2C_ADDR
|
|
|
|
|
CONFIG_POWER_PFUZE100
|
|
|
|
|
CONFIG_POWER_PFUZE100_I2C_ADDR
|
|
|
|
|
CONFIG_POWER_PFUZE3000
|
|
|
|
|
CONFIG_POWER_PFUZE3000_I2C_ADDR
|
|
|
|
|
CONFIG_POWER_SPI
|
|
|
|
|
CONFIG_POWER_TPS62362
|
|
|
|
|
CONFIG_POWER_TPS65090_EC
|
|
|
|
|
CONFIG_POWER_TPS65218
|
|
|
|
|
CONFIG_POWER_TPS65910
|
|
|
|
|
CONFIG_PPC_SPINTABLE_COMPATIBLE
|
|
|
|
|
CONFIG_PRAM
|
|
|
|
|
CONFIG_PSRAM_SCFG
|
|
|
|
|
CONFIG_QBMAN_CLK_DIV
|
|
|
|
|
CONFIG_RAMBOOT_SPIFLASH
|
|
|
|
|
CONFIG_RAMBOOT_TEXT_BASE
|
|
|
|
|
CONFIG_RAMDISK_ADDR
|
|
|
|
|
CONFIG_RD_LVL
|
|
|
|
|
CONFIG_RESET_VECTOR_ADDRESS
|
|
|
|
|
CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
|
|
|
|
|
CONFIG_ROOTPATH
|
|
|
|
|
CONFIG_RTC_DS1337
|
2017-05-30 00:03:33 +00:00
|
|
|
CONFIG_RTC_DS1337_NOOSC
|
2016-09-14 03:44:06 +00:00
|
|
|
CONFIG_RTC_DS1338
|
|
|
|
|
CONFIG_RTC_DS1374
|
|
|
|
|
CONFIG_RTC_DS3231
|
|
|
|
|
CONFIG_RTC_MC13XXX
|
|
|
|
|
CONFIG_RTC_MCFRRTC
|
|
|
|
|
CONFIG_RTC_MXS
|
|
|
|
|
CONFIG_RTC_PT7C4338
|
|
|
|
|
CONFIG_SAMA5D3_LCD_BASE
|
|
|
|
|
CONFIG_SANDBOX_ARCH
|
|
|
|
|
CONFIG_SANDBOX_SDL
|
|
|
|
|
CONFIG_SANDBOX_SPI_MAX_BUS
|
|
|
|
|
CONFIG_SANDBOX_SPI_MAX_CS
|
|
|
|
|
CONFIG_SAR2_REG
|
|
|
|
|
CONFIG_SAR_REG
|
|
|
|
|
CONFIG_SCIF_A
|
|
|
|
|
CONFIG_SCSI_DEV_LIST
|
|
|
|
|
CONFIG_SC_TIMER_CLK
|
|
|
|
|
CONFIG_SERIAL_BOOT
|
|
|
|
|
CONFIG_SERIAL_SOFTWARE_FIFO
|
|
|
|
|
CONFIG_SERVERIP
|
|
|
|
|
CONFIG_SETUP_INITRD_TAG
|
|
|
|
|
CONFIG_SET_DFU_ALT_BUF_LEN
|
|
|
|
|
CONFIG_SH_ETHER_ALIGNE_SIZE
|
|
|
|
|
CONFIG_SH_ETHER_CACHE_INVALIDATE
|
|
|
|
|
CONFIG_SH_ETHER_CACHE_WRITEBACK
|
|
|
|
|
CONFIG_SH_ETHER_PHY_ADDR
|
|
|
|
|
CONFIG_SH_ETHER_PHY_MODE
|
|
|
|
|
CONFIG_SH_ETHER_SH7734_MII
|
|
|
|
|
CONFIG_SH_ETHER_USE_PORT
|
|
|
|
|
CONFIG_SH_GPIO_PFC
|
|
|
|
|
CONFIG_SH_QSPI_BASE
|
|
|
|
|
CONFIG_SLIC
|
|
|
|
|
CONFIG_SMDK5420
|
|
|
|
|
CONFIG_SMP_PEN_ADDR
|
|
|
|
|
CONFIG_SMSC_LPC47M
|
|
|
|
|
CONFIG_SMSC_SIO1007
|
|
|
|
|
CONFIG_SOCRATES
|
|
|
|
|
CONFIG_SOFT_I2C_READ_REPEATED_START
|
|
|
|
|
CONFIG_SPD_EEPROM
|
|
|
|
|
CONFIG_SPI_ADDR
|
|
|
|
|
CONFIG_SPI_BOOTING
|
|
|
|
|
CONFIG_SPI_FLASH_QUAD
|
|
|
|
|
CONFIG_SPI_FLASH_SIZE
|
|
|
|
|
CONFIG_SPI_HALF_DUPLEX
|
|
|
|
|
CONFIG_SPI_N25Q256A_RESET
|
|
|
|
|
CONFIG_SRIO1
|
|
|
|
|
CONFIG_SRIO2
|
|
|
|
|
CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET
|
|
|
|
|
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1
|
|
|
|
|
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2
|
|
|
|
|
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS
|
|
|
|
|
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE
|
|
|
|
|
CONFIG_SRIO_PCIE_BOOT_MASTER
|
|
|
|
|
CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK
|
|
|
|
|
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS
|
|
|
|
|
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
|
|
|
|
|
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
|
|
|
|
|
CONFIG_STACKBASE
|
|
|
|
|
CONFIG_STANDALONE_LOAD_ADDR
|
|
|
|
|
CONFIG_STD_DEVICES_SETTINGS
|
|
|
|
|
CONFIG_SYS_AMASK0
|
|
|
|
|
CONFIG_SYS_AMASK1
|
|
|
|
|
CONFIG_SYS_AMASK1_FINAL
|
|
|
|
|
CONFIG_SYS_AMASK2
|
|
|
|
|
CONFIG_SYS_AMASK2_FINAL
|
|
|
|
|
CONFIG_SYS_AMASK3
|
|
|
|
|
CONFIG_SYS_AMASK4
|
|
|
|
|
CONFIG_SYS_AMASK6
|
|
|
|
|
CONFIG_SYS_AMASK7
|
|
|
|
|
CONFIG_SYS_AT91_MAIN_CLOCK
|
|
|
|
|
CONFIG_SYS_AT91_PLLA
|
|
|
|
|
CONFIG_SYS_AT91_PLLB
|
|
|
|
|
CONFIG_SYS_AT91_SLOW_CLOCK
|
|
|
|
|
CONFIG_SYS_BAUDRATE_TABLE
|
|
|
|
|
CONFIG_SYS_BMAN_CENA_BASE
|
|
|
|
|
CONFIG_SYS_BMAN_CENA_SIZE
|
|
|
|
|
CONFIG_SYS_BMAN_CINH_BASE
|
|
|
|
|
CONFIG_SYS_BMAN_CINH_SIZE
|
|
|
|
|
CONFIG_SYS_BMAN_MEM_BASE
|
|
|
|
|
CONFIG_SYS_BMAN_MEM_PHYS
|
|
|
|
|
CONFIG_SYS_BMAN_MEM_SIZE
|
|
|
|
|
CONFIG_SYS_BMAN_NUM_PORTALS
|
|
|
|
|
CONFIG_SYS_BMAN_SP_CENA_SIZE
|
|
|
|
|
CONFIG_SYS_BMAN_SP_CINH_SIZE
|
|
|
|
|
CONFIG_SYS_BMAN_SWP_ISDR_REG
|
|
|
|
|
CONFIG_SYS_BOOTMAPSZ
|
|
|
|
|
CONFIG_SYS_CACHE_ACR0
|
|
|
|
|
CONFIG_SYS_CACHE_ACR1
|
|
|
|
|
CONFIG_SYS_CACHE_ACR2
|
|
|
|
|
CONFIG_SYS_CACHE_DCACR
|
|
|
|
|
CONFIG_SYS_CACHE_ICACR
|
|
|
|
|
CONFIG_SYS_CCSRBAR
|
|
|
|
|
CONFIG_SYS_CCSRBAR_PHYS
|
|
|
|
|
CONFIG_SYS_CCSRBAR_PHYS_HIGH
|
|
|
|
|
CONFIG_SYS_CCSRBAR_PHYS_LOW
|
|
|
|
|
CONFIG_SYS_CLK
|
|
|
|
|
CONFIG_SYS_CLKTL_CBCDR
|
|
|
|
|
CONFIG_SYS_CPLD_AMASK
|
|
|
|
|
CONFIG_SYS_CPLD_BASE
|
|
|
|
|
CONFIG_SYS_CPLD_BASE_PHYS
|
|
|
|
|
CONFIG_SYS_CPLD_CSOR
|
|
|
|
|
CONFIG_SYS_CPLD_CSPR
|
|
|
|
|
CONFIG_SYS_CPLD_CSPR_EXT
|
|
|
|
|
CONFIG_SYS_CPLD_FTIM0
|
|
|
|
|
CONFIG_SYS_CPLD_FTIM1
|
|
|
|
|
CONFIG_SYS_CPLD_FTIM2
|
|
|
|
|
CONFIG_SYS_CPLD_FTIM3
|
|
|
|
|
CONFIG_SYS_CPU_CLK
|
|
|
|
|
CONFIG_SYS_CS0_BASE
|
|
|
|
|
CONFIG_SYS_CS0_CTRL
|
|
|
|
|
CONFIG_SYS_CS0_FTIM0
|
|
|
|
|
CONFIG_SYS_CS0_FTIM1
|
|
|
|
|
CONFIG_SYS_CS0_FTIM2
|
|
|
|
|
CONFIG_SYS_CS0_FTIM3
|
|
|
|
|
CONFIG_SYS_CS0_MASK
|
|
|
|
|
CONFIG_SYS_CS1_BASE
|
|
|
|
|
CONFIG_SYS_CS1_CTRL
|
|
|
|
|
CONFIG_SYS_CS1_FTIM0
|
|
|
|
|
CONFIG_SYS_CS1_FTIM1
|
|
|
|
|
CONFIG_SYS_CS1_FTIM2
|
|
|
|
|
CONFIG_SYS_CS1_FTIM3
|
|
|
|
|
CONFIG_SYS_CS1_MASK
|
|
|
|
|
CONFIG_SYS_CS2_BASE
|
|
|
|
|
CONFIG_SYS_CS2_CTRL
|
|
|
|
|
CONFIG_SYS_CS2_FTIM0
|
|
|
|
|
CONFIG_SYS_CS2_FTIM1
|
|
|
|
|
CONFIG_SYS_CS2_FTIM2
|
|
|
|
|
CONFIG_SYS_CS2_FTIM3
|
|
|
|
|
CONFIG_SYS_CS2_MASK
|
|
|
|
|
CONFIG_SYS_CS3_BASE
|
|
|
|
|
CONFIG_SYS_CS3_CTRL
|
|
|
|
|
CONFIG_SYS_CS3_FTIM0
|
|
|
|
|
CONFIG_SYS_CS3_FTIM1
|
|
|
|
|
CONFIG_SYS_CS3_FTIM2
|
|
|
|
|
CONFIG_SYS_CS3_FTIM3
|
|
|
|
|
CONFIG_SYS_CS3_MASK
|
|
|
|
|
CONFIG_SYS_CS4_FTIM0
|
|
|
|
|
CONFIG_SYS_CS4_FTIM1
|
|
|
|
|
CONFIG_SYS_CS4_FTIM2
|
|
|
|
|
CONFIG_SYS_CS4_FTIM3
|
|
|
|
|
CONFIG_SYS_CS6_FTIM0
|
|
|
|
|
CONFIG_SYS_CS6_FTIM1
|
|
|
|
|
CONFIG_SYS_CS6_FTIM2
|
|
|
|
|
CONFIG_SYS_CS6_FTIM3
|
|
|
|
|
CONFIG_SYS_CS7_FTIM0
|
|
|
|
|
CONFIG_SYS_CS7_FTIM1
|
|
|
|
|
CONFIG_SYS_CS7_FTIM2
|
|
|
|
|
CONFIG_SYS_CS7_FTIM3
|
|
|
|
|
CONFIG_SYS_CSOR0
|
|
|
|
|
CONFIG_SYS_CSOR1
|
|
|
|
|
CONFIG_SYS_CSOR2
|
|
|
|
|
CONFIG_SYS_CSOR3
|
|
|
|
|
CONFIG_SYS_CSOR4
|
|
|
|
|
CONFIG_SYS_CSOR6
|
|
|
|
|
CONFIG_SYS_CSOR7
|
|
|
|
|
CONFIG_SYS_CSPR0
|
|
|
|
|
CONFIG_SYS_CSPR0_EXT
|
|
|
|
|
CONFIG_SYS_CSPR0_FINAL
|
|
|
|
|
CONFIG_SYS_CSPR1
|
|
|
|
|
CONFIG_SYS_CSPR1_EXT
|
|
|
|
|
CONFIG_SYS_CSPR1_FINAL
|
|
|
|
|
CONFIG_SYS_CSPR2
|
|
|
|
|
CONFIG_SYS_CSPR2_EXT
|
|
|
|
|
CONFIG_SYS_CSPR2_FINAL
|
|
|
|
|
CONFIG_SYS_CSPR3
|
|
|
|
|
CONFIG_SYS_CSPR3_EXT
|
|
|
|
|
CONFIG_SYS_CSPR3_FINAL
|
|
|
|
|
CONFIG_SYS_CSPR4
|
|
|
|
|
CONFIG_SYS_CSPR4_EXT
|
|
|
|
|
CONFIG_SYS_CSPR6
|
|
|
|
|
CONFIG_SYS_CSPR6_EXT
|
|
|
|
|
CONFIG_SYS_CSPR7
|
|
|
|
|
CONFIG_SYS_CSPR7_EXT
|
|
|
|
|
CONFIG_SYS_DA850_DDR2_DDRPHYCR
|
|
|
|
|
CONFIG_SYS_DA850_DDR2_PBBPR
|
|
|
|
|
CONFIG_SYS_DA850_DDR2_SDBCR
|
|
|
|
|
CONFIG_SYS_DA850_DDR2_SDBCR2
|
|
|
|
|
CONFIG_SYS_DA850_DDR2_SDRCR
|
|
|
|
|
CONFIG_SYS_DA850_DDR2_SDTIMR
|
|
|
|
|
CONFIG_SYS_DA850_DDR2_SDTIMR2
|
|
|
|
|
CONFIG_SYS_DA850_PLL0_PLLM
|
|
|
|
|
CONFIG_SYS_DA850_PLL1_PLLM
|
|
|
|
|
CONFIG_SYS_DA850_SYSCFG_SUSPSRC
|
|
|
|
|
CONFIG_SYS_DCACHE_INV
|
|
|
|
|
CONFIG_SYS_DCSRBAR
|
|
|
|
|
CONFIG_SYS_DCSRBAR_PHYS
|
|
|
|
|
CONFIG_SYS_DCSR_DCFG_ADDR
|
|
|
|
|
CONFIG_SYS_DCSR_DCFG_OFFSET
|
|
|
|
|
CONFIG_SYS_DDRCDR
|
|
|
|
|
CONFIG_SYS_DDRCDR_VALUE
|
|
|
|
|
CONFIG_SYS_DDRUA
|
|
|
|
|
CONFIG_SYS_DDR_BLOCK1_SIZE
|
|
|
|
|
CONFIG_SYS_DDR_BLOCK2_BASE
|
|
|
|
|
CONFIG_SYS_DDR_CLKSEL
|
|
|
|
|
CONFIG_SYS_DDR_CLK_CNTL
|
|
|
|
|
CONFIG_SYS_DDR_CLK_CONTROL
|
|
|
|
|
CONFIG_SYS_DDR_CLK_CTRL
|
|
|
|
|
CONFIG_SYS_DDR_CONFIG
|
|
|
|
|
CONFIG_SYS_DDR_CONFIG_2
|
|
|
|
|
CONFIG_SYS_DDR_CONTROL
|
|
|
|
|
CONFIG_SYS_DDR_CONTROL_2
|
|
|
|
|
CONFIG_SYS_DDR_CS0_BNDS
|
|
|
|
|
CONFIG_SYS_DDR_CS0_CONFIG
|
|
|
|
|
CONFIG_SYS_DDR_CS0_CONFIG_2
|
|
|
|
|
CONFIG_SYS_DDR_CS1_BNDS
|
|
|
|
|
CONFIG_SYS_DDR_CS1_CONFIG
|
|
|
|
|
CONFIG_SYS_DDR_CS1_CONFIG_2
|
|
|
|
|
CONFIG_SYS_DDR_INIT_ADDR
|
|
|
|
|
CONFIG_SYS_DDR_INIT_EXT_ADDR
|
|
|
|
|
CONFIG_SYS_DDR_INTERVAL
|
|
|
|
|
CONFIG_SYS_DDR_MODE
|
|
|
|
|
CONFIG_SYS_DDR_MODE2
|
|
|
|
|
CONFIG_SYS_DDR_MODE_1
|
|
|
|
|
CONFIG_SYS_DDR_MODE_2
|
|
|
|
|
CONFIG_SYS_DDR_MODE_CONTROL
|
|
|
|
|
CONFIG_SYS_DDR_RCW_1
|
|
|
|
|
CONFIG_SYS_DDR_RCW_2
|
|
|
|
|
CONFIG_SYS_DDR_SDRAM_BASE
|
|
|
|
|
CONFIG_SYS_DDR_SDRAM_CFG
|
|
|
|
|
CONFIG_SYS_DDR_SDRAM_CFG2
|
|
|
|
|
CONFIG_SYS_DDR_SDRAM_CLK_CNTL
|
|
|
|
|
CONFIG_SYS_DDR_SR_CNTR
|
|
|
|
|
CONFIG_SYS_DDR_TIMING_0
|
|
|
|
|
CONFIG_SYS_DDR_TIMING_1
|
|
|
|
|
CONFIG_SYS_DDR_TIMING_2
|
|
|
|
|
CONFIG_SYS_DDR_TIMING_3
|
|
|
|
|
CONFIG_SYS_DDR_TIMING_4
|
|
|
|
|
CONFIG_SYS_DDR_TIMING_5
|
|
|
|
|
CONFIG_SYS_DDR_WRLVL_CONTROL
|
|
|
|
|
CONFIG_SYS_DDR_ZQ_CONTROL
|
|
|
|
|
CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
|
|
|
|
|
CONFIG_SYS_DPAA_DCE
|
|
|
|
|
CONFIG_SYS_DPAA_FMAN
|
|
|
|
|
CONFIG_SYS_DPAA_PME
|
|
|
|
|
CONFIG_SYS_DPAA_RMAN
|
|
|
|
|
CONFIG_SYS_DRAM_TEST
|
|
|
|
|
CONFIG_SYS_DV_NOR_BOOT_CFG
|
|
|
|
|
CONFIG_SYS_EEPROM_WREN
|
|
|
|
|
CONFIG_SYS_ENV_SECT_SIZE
|
|
|
|
|
CONFIG_SYS_ETHOC_BASE
|
|
|
|
|
CONFIG_SYS_ETHOC_BUFFER_ADDR
|
|
|
|
|
CONFIG_SYS_EXCEPTION_VECTORS_HIGH
|
|
|
|
|
CONFIG_SYS_FAST_CLK
|
|
|
|
|
CONFIG_SYS_FEC_BUF_USE_SRAM
|
|
|
|
|
CONFIG_SYS_FLASH0
|
|
|
|
|
CONFIG_SYS_FLASH1
|
|
|
|
|
CONFIG_SYS_FLASH1_BASE_PHYS
|
|
|
|
|
CONFIG_SYS_FLASH1_BASE_PHYS_EARLY
|
|
|
|
|
CONFIG_SYS_FLASH_BANKS_LIST
|
|
|
|
|
CONFIG_SYS_FLASH_BANKS_SIZES
|
|
|
|
|
CONFIG_SYS_FLASH_BASE
|
|
|
|
|
CONFIG_SYS_FLASH_BASE_PHYS
|
|
|
|
|
CONFIG_SYS_FLASH_BASE_PHYS_EARLY
|
|
|
|
|
CONFIG_SYS_FLASH_PARMSECT_SZ
|
|
|
|
|
CONFIG_SYS_FLASH_SIZE
|
|
|
|
|
CONFIG_SYS_FM1_10GEC1_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_CLK
|
|
|
|
|
CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_DTSEC2_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_DTSEC3_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_DTSEC4_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_QSGMII11_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM1_QSGMII21_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_FM2_CLK
|
|
|
|
|
CONFIG_SYS_FM_MURAM_SIZE
|
|
|
|
|
CONFIG_SYS_FPGAREG_DIPSW
|
|
|
|
|
CONFIG_SYS_FPGAREG_FREQ
|
|
|
|
|
CONFIG_SYS_FPGAREG_RESET
|
|
|
|
|
CONFIG_SYS_FPGAREG_RESET_CODE
|
|
|
|
|
CONFIG_SYS_FPGA_AMASK
|
|
|
|
|
CONFIG_SYS_FPGA_BASE
|
|
|
|
|
CONFIG_SYS_FPGA_CSOR
|
|
|
|
|
CONFIG_SYS_FPGA_CSPR
|
|
|
|
|
CONFIG_SYS_FPGA_CSPR_EXT
|
|
|
|
|
CONFIG_SYS_FPGA_FTIM0
|
|
|
|
|
CONFIG_SYS_FPGA_FTIM1
|
|
|
|
|
CONFIG_SYS_FPGA_FTIM2
|
|
|
|
|
CONFIG_SYS_FPGA_FTIM3
|
|
|
|
|
CONFIG_SYS_FPGA_SIZE
|
|
|
|
|
CONFIG_SYS_FPGA_WAIT
|
|
|
|
|
CONFIG_SYS_FSL_BMAN_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_BMAN_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CLK_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CLUSTER_1_L2
|
|
|
|
|
CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CLUSTER_CLOCKS
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_CCM_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_CCM_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_CLK_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_CLK_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_PMAN
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_PME_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_PME_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_RCPM_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_RCPM_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_RMAN_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_RMAN_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_SERDES2_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_SERDES3_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_SERDES4_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_SERDES_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_SERDES_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
|
|
|
|
|
CONFIG_SYS_FSL_CPC_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_CPC_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_CSU_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_DCSR_DDR2_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_DCSR_DDR3_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_DCSR_DDR_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_DDR2_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_DDR3_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_DDR_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
|
|
|
|
|
CONFIG_SYS_FSL_ESDHC_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_FM
|
|
|
|
|
CONFIG_SYS_FSL_FM1_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_FM1_DTSEC1_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM1_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM2_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_FM2_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_GUTS_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_JR0_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_JR0_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_LS1_CLK_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_NUM_CC_PLL
|
|
|
|
|
CONFIG_SYS_FSL_OCRAM_BASE
|
|
|
|
|
CONFIG_SYS_FSL_OCRAM_SIZE
|
|
|
|
|
CONFIG_SYS_FSL_PAMU_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_PMIC_I2C_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_PMU_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_PMU_CLTBENR
|
|
|
|
|
CONFIG_SYS_FSL_QMAN_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_QMAN_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_QSPI_BASE
|
|
|
|
|
CONFIG_SYS_FSL_RAID_ENGINE_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_RAID_ENGINE_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_RCPM_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_RST_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_SCFG_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_SCFG_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_SEC_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_SEC_IDX_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_SEC_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_SERDES
|
|
|
|
|
CONFIG_SYS_FSL_SERDES_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_SRDS_3
|
|
|
|
|
CONFIG_SYS_FSL_SRDS_4
|
|
|
|
|
CONFIG_SYS_FSL_SRIO_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_SRIO_IB_WIN_NUM
|
|
|
|
|
CONFIG_SYS_FSL_SRIO_MAX_PORTS
|
|
|
|
|
CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM
|
|
|
|
|
CONFIG_SYS_FSL_SRIO_OB_WIN_NUM
|
|
|
|
|
CONFIG_SYS_FSL_SRIO_OFFSET
|
|
|
|
|
CONFIG_SYS_FSL_TIMER_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_USDHC_NUM
|
|
|
|
|
CONFIG_SYS_FSL_WRIOP1_ADDR
|
|
|
|
|
CONFIG_SYS_FSL_WRIOP1_MDIO1
|
|
|
|
|
CONFIG_SYS_FSL_WRIOP1_MDIO2
|
|
|
|
|
CONFIG_SYS_GPIO1_EN
|
|
|
|
|
CONFIG_SYS_GPIO1_FUNC
|
|
|
|
|
CONFIG_SYS_GPIO1_LED
|
|
|
|
|
CONFIG_SYS_GPIO1_OUT
|
|
|
|
|
CONFIG_SYS_GPIO_EN
|
|
|
|
|
CONFIG_SYS_GPIO_FUNC
|
|
|
|
|
CONFIG_SYS_GPIO_OUT
|
|
|
|
|
CONFIG_SYS_GPR1
|
|
|
|
|
CONFIG_SYS_HZ_CLOCK
|
|
|
|
|
CONFIG_SYS_I2C_BUSES
|
|
|
|
|
CONFIG_SYS_I2C_EXPANDER_ADDR
|
|
|
|
|
CONFIG_SYS_I2C_FPGA_ADDR
|
|
|
|
|
CONFIG_SYS_I2C_G762_ADDR
|
|
|
|
|
CONFIG_SYS_I2C_IFDR_DIV
|
|
|
|
|
CONFIG_SYS_I2C_INIT_BOARD
|
|
|
|
|
CONFIG_SYS_I2C_MAX_HOPS
|
|
|
|
|
CONFIG_SYS_I2C_NOPROBES
|
|
|
|
|
CONFIG_SYS_I2C_PCA953X_ADDR
|
|
|
|
|
CONFIG_SYS_I2C_PCA953X_WIDTH
|
|
|
|
|
CONFIG_SYS_I2C_PCA9557_ADDR
|
|
|
|
|
CONFIG_SYS_I2C_PINMUX_CLR
|
|
|
|
|
CONFIG_SYS_I2C_PINMUX_REG
|
|
|
|
|
CONFIG_SYS_I2C_PINMUX_SET
|
|
|
|
|
CONFIG_SYS_I2C_RTC_ADDR
|
|
|
|
|
CONFIG_SYS_I2C_TCA642X_ADDR
|
|
|
|
|
CONFIG_SYS_I2C_TCA642X_BUS_NUM
|
|
|
|
|
CONFIG_SYS_ICACHE_INV
|
|
|
|
|
CONFIG_SYS_IFC_ADDR
|
|
|
|
|
CONFIG_SYS_IFC_CCR
|
|
|
|
|
CONFIG_SYS_INIT_DBCR
|
|
|
|
|
CONFIG_SYS_INIT_L2CSR0
|
|
|
|
|
CONFIG_SYS_INIT_L2_ADDR
|
|
|
|
|
CONFIG_SYS_INIT_L2_ADDR_PHYS
|
|
|
|
|
CONFIG_SYS_INIT_L2_END
|
|
|
|
|
CONFIG_SYS_INIT_L3_ADDR
|
|
|
|
|
CONFIG_SYS_INIT_L3_ADDR_PHYS
|
|
|
|
|
CONFIG_SYS_INIT_L3_END
|
|
|
|
|
CONFIG_SYS_INIT_L3_VADDR
|
|
|
|
|
CONFIG_SYS_INIT_RAM_ADDR
|
|
|
|
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS
|
|
|
|
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
|
|
|
|
|
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW
|
|
|
|
|
CONFIG_SYS_INIT_RAM_CTRL
|
|
|
|
|
CONFIG_SYS_INIT_RAM_LOCK
|
|
|
|
|
CONFIG_SYS_INIT_RAM_SIZE
|
|
|
|
|
CONFIG_SYS_INIT_SP_OFFSET
|
|
|
|
|
CONFIG_SYS_INTERLAKEN
|
|
|
|
|
CONFIG_SYS_INT_FLASH_BASE
|
|
|
|
|
CONFIG_SYS_INT_FLASH_ENABLE
|
|
|
|
|
CONFIG_SYS_IO_BASE
|
|
|
|
|
CONFIG_SYS_ISA_IO
|
|
|
|
|
CONFIG_SYS_ISA_IO_BASE_ADDRESS
|
|
|
|
|
CONFIG_SYS_JFFS2_FIRST_BANK
|
|
|
|
|
CONFIG_SYS_JFFS2_FIRST_SECTOR
|
|
|
|
|
CONFIG_SYS_JFFS2_NUM_BANKS
|
|
|
|
|
CONFIG_SYS_KMBEC_FPGA_BASE
|
|
|
|
|
CONFIG_SYS_KMBEC_FPGA_SIZE
|
|
|
|
|
CONFIG_SYS_L2_SIZE
|
|
|
|
|
CONFIG_SYS_L3_SIZE
|
|
|
|
|
CONFIG_SYS_LATCH_ADDR
|
|
|
|
|
CONFIG_SYS_LBC_ADDR
|
|
|
|
|
CONFIG_SYS_LBC_CACHE_BASE
|
|
|
|
|
CONFIG_SYS_LBC_FLASH_BASE
|
|
|
|
|
CONFIG_SYS_LBC_LBCR
|
|
|
|
|
CONFIG_SYS_LBC_LCRR
|
|
|
|
|
CONFIG_SYS_LBC_LSDMR_COMMON
|
|
|
|
|
CONFIG_SYS_LBC_LSRT
|
|
|
|
|
CONFIG_SYS_LBC_MRTPR
|
|
|
|
|
CONFIG_SYS_LBC_SDRAM_BASE
|
|
|
|
|
CONFIG_SYS_LBC_SDRAM_BASE_PHYS
|
|
|
|
|
CONFIG_SYS_LBC_SDRAM_SIZE
|
|
|
|
|
CONFIG_SYS_LDB_CLOCK
|
|
|
|
|
CONFIG_SYS_LIME_BASE
|
|
|
|
|
CONFIG_SYS_LIME_SIZE
|
|
|
|
|
CONFIG_SYS_LOADS_BAUD_CHANGE
|
|
|
|
|
CONFIG_SYS_LOW
|
|
|
|
|
CONFIG_SYS_LOWMEM_BASE
|
|
|
|
|
CONFIG_SYS_LPAE_SDRAM_BASE
|
|
|
|
|
CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
|
|
|
|
|
CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
|
|
|
|
|
CONFIG_SYS_LS_MC_DPC_MAX_LENGTH
|
|
|
|
|
CONFIG_SYS_LS_MC_DPL_MAX_LENGTH
|
|
|
|
|
CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
|
|
|
|
|
CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
|
|
|
|
|
CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET
|
|
|
|
|
CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET
|
|
|
|
|
CONFIG_SYS_M41T11_BASE_YEAR
|
|
|
|
|
CONFIG_SYS_MAIN_PWR_ON
|
|
|
|
|
CONFIG_SYS_MAMR
|
|
|
|
|
CONFIG_SYS_MASTER_CLOCK
|
|
|
|
|
CONFIG_SYS_MATRIX_EBI0CSA_VAL
|
|
|
|
|
CONFIG_SYS_MATRIX_EBICSA_VAL
|
|
|
|
|
CONFIG_SYS_MAX_I2C_BUS
|
|
|
|
|
CONFIG_SYS_MAX_NAND_CHIPS
|
|
|
|
|
CONFIG_SYS_MAX_NAND_DEVICE
|
|
|
|
|
CONFIG_SYS_MBAR
|
|
|
|
|
CONFIG_SYS_MBAR2
|
|
|
|
|
CONFIG_SYS_MCFRRTC_BASE
|
|
|
|
|
CONFIG_SYS_MCKR
|
|
|
|
|
CONFIG_SYS_MCKR1_VAL
|
|
|
|
|
CONFIG_SYS_MCKR2_VAL
|
|
|
|
|
CONFIG_SYS_MCKR_CSS
|
|
|
|
|
CONFIG_SYS_MDIO1_OFFSET
|
|
|
|
|
CONFIG_SYS_MEMORY_BASE
|
|
|
|
|
CONFIG_SYS_MEM_RESERVE_SECURE
|
|
|
|
|
CONFIG_SYS_MFD
|
|
|
|
|
CONFIG_SYS_MHZ
|
|
|
|
|
CONFIG_SYS_MIPS_TIMER_FREQ
|
|
|
|
|
CONFIG_SYS_MMC_CD_PIN
|
|
|
|
|
CONFIG_SYS_MMC_CLK_OD
|
|
|
|
|
CONFIG_SYS_MMC_MAX_BLK_COUNT
|
|
|
|
|
CONFIG_SYS_MMC_MAX_DEVICE
|
|
|
|
|
CONFIG_SYS_MMC_U_BOOT_DST
|
|
|
|
|
CONFIG_SYS_MMC_U_BOOT_OFFS
|
|
|
|
|
CONFIG_SYS_MMC_U_BOOT_SIZE
|
|
|
|
|
CONFIG_SYS_MMC_U_BOOT_START
|
|
|
|
|
CONFIG_SYS_MONITOR_LEN
|
|
|
|
|
CONFIG_SYS_MONITOR_SEC
|
|
|
|
|
CONFIG_SYS_MOR_VAL
|
|
|
|
|
CONFIG_SYS_MPC83xx_DMA_ADDR
|
|
|
|
|
CONFIG_SYS_MPC83xx_DMA_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC83xx_ESDHC_ADDR
|
|
|
|
|
CONFIG_SYS_MPC83xx_ESDHC_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_DMA
|
|
|
|
|
CONFIG_SYS_MPC85xx_DMA1_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_DMA2_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_DMA3_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_DMA_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_DMA_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_ECM_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_ECM_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_ESDHC_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_ESPI_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_ESPI_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_GPIO_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_GPIO_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_GUTS_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_GUTS_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_IFC_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_L2_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_L2_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_LBC_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCI1_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCI2_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCIE
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCIE1_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCIE2_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCIE3_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCIE4_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCIX2_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCIX2_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCIX_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_PCIX_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_PIC_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_QE_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_SATA
|
|
|
|
|
CONFIG_SYS_MPC85xx_SATA1_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_SATA1_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_SATA2_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_SATA2_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_SCFG
|
|
|
|
|
CONFIG_SYS_MPC85xx_SCFG_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_SERDES1_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_SERDES1_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_SERDES2_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_SERDES2_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_TDM_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_USB
|
|
|
|
|
CONFIG_SYS_MPC85xx_USB1_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_USB1_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_USB1_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_USB2_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_USB2_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC85xx_USB2_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC8xxx_DDR2_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC8xxx_DDR3_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC8xxx_DDR_OFFSET
|
|
|
|
|
CONFIG_SYS_MPC8xxx_PIC_ADDR
|
|
|
|
|
CONFIG_SYS_MRAM_BASE
|
|
|
|
|
CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
|
|
|
|
|
CONFIG_SYS_NAND_AMASK
|
|
|
|
|
CONFIG_SYS_NAND_BASE
|
|
|
|
|
CONFIG_SYS_NAND_BASE2
|
|
|
|
|
CONFIG_SYS_NAND_BASE_LIST
|
|
|
|
|
CONFIG_SYS_NAND_BASE_PHYS
|
|
|
|
|
CONFIG_SYS_NAND_BR_PRELIM
|
|
|
|
|
CONFIG_SYS_NAND_CS
|
|
|
|
|
CONFIG_SYS_NAND_CSOR
|
|
|
|
|
CONFIG_SYS_NAND_CSPR
|
|
|
|
|
CONFIG_SYS_NAND_CSPR_EXT
|
|
|
|
|
CONFIG_SYS_NAND_DATA_BASE
|
|
|
|
|
CONFIG_SYS_NAND_DBW_8
|
|
|
|
|
CONFIG_SYS_NAND_DDR_LAW
|
|
|
|
|
CONFIG_SYS_NAND_ECCBYTES
|
|
|
|
|
CONFIG_SYS_NAND_ECCPOS
|
|
|
|
|
CONFIG_SYS_NAND_ECCSIZE
|
|
|
|
|
CONFIG_SYS_NAND_ECCSTEPS
|
|
|
|
|
CONFIG_SYS_NAND_ECCTOTAL
|
|
|
|
|
CONFIG_SYS_NAND_ECC_BASE
|
|
|
|
|
CONFIG_SYS_NAND_ENABLE_PIN
|
|
|
|
|
CONFIG_SYS_NAND_ENABLE_PIN_SPL
|
|
|
|
|
CONFIG_SYS_NAND_FTIM0
|
|
|
|
|
CONFIG_SYS_NAND_FTIM1
|
|
|
|
|
CONFIG_SYS_NAND_FTIM2
|
|
|
|
|
CONFIG_SYS_NAND_FTIM3
|
|
|
|
|
CONFIG_SYS_NAND_HW_ECC
|
|
|
|
|
CONFIG_SYS_NAND_HW_ECC_OOBFIRST
|
|
|
|
|
CONFIG_SYS_NAND_LARGEPAGE
|
|
|
|
|
CONFIG_SYS_NAND_MASK_ALE
|
|
|
|
|
CONFIG_SYS_NAND_MASK_CLE
|
|
|
|
|
CONFIG_SYS_NAND_MAX_ECCPOS
|
|
|
|
|
CONFIG_SYS_NAND_MAX_OOBFREE
|
|
|
|
|
CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
|
|
|
|
|
CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
|
|
|
|
|
CONFIG_SYS_NAND_OR_PRELIM
|
|
|
|
|
CONFIG_SYS_NAND_PAGE_2K
|
|
|
|
|
CONFIG_SYS_NAND_PAGE_4K
|
|
|
|
|
CONFIG_SYS_NAND_READY_PIN
|
|
|
|
|
CONFIG_SYS_NAND_REGS_BASE
|
|
|
|
|
CONFIG_SYS_NAND_SIZE
|
|
|
|
|
CONFIG_SYS_NAND_U_BOOT_DST
|
|
|
|
|
CONFIG_SYS_NAND_U_BOOT_RELOC_SP
|
|
|
|
|
CONFIG_SYS_NAND_U_BOOT_SIZE
|
|
|
|
|
CONFIG_SYS_NAND_U_BOOT_START
|
|
|
|
|
CONFIG_SYS_NONCACHED_MEMORY
|
|
|
|
|
CONFIG_SYS_NOR0_CSPR
|
|
|
|
|
CONFIG_SYS_NOR0_CSPR_EARLY
|
|
|
|
|
CONFIG_SYS_NOR0_CSPR_EXT
|
|
|
|
|
CONFIG_SYS_NOR1_CSPR
|
|
|
|
|
CONFIG_SYS_NOR1_CSPR_EARLY
|
|
|
|
|
CONFIG_SYS_NOR1_CSPR_EXT
|
|
|
|
|
CONFIG_SYS_NOR_AMASK
|
|
|
|
|
CONFIG_SYS_NOR_AMASK_EARLY
|
|
|
|
|
CONFIG_SYS_NOR_CSOR
|
|
|
|
|
CONFIG_SYS_NOR_CSPR
|
|
|
|
|
CONFIG_SYS_NOR_CSPR_EXT
|
|
|
|
|
CONFIG_SYS_NOR_FTIM0
|
|
|
|
|
CONFIG_SYS_NOR_FTIM1
|
|
|
|
|
CONFIG_SYS_NOR_FTIM2
|
|
|
|
|
CONFIG_SYS_NOR_FTIM3
|
|
|
|
|
CONFIG_SYS_NS16550_CLK
|
|
|
|
|
CONFIG_SYS_NS16550_COM1
|
|
|
|
|
CONFIG_SYS_NS16550_COM2
|
|
|
|
|
CONFIG_SYS_NS16550_COM3
|
|
|
|
|
CONFIG_SYS_NS16550_COM4
|
|
|
|
|
CONFIG_SYS_NS16550_COM5
|
|
|
|
|
CONFIG_SYS_NS16550_COM6
|
|
|
|
|
CONFIG_SYS_NS16550_MEM32
|
|
|
|
|
CONFIG_SYS_NS16550_PORT_MAPPED
|
|
|
|
|
CONFIG_SYS_NS16550_REG_SIZE
|
|
|
|
|
CONFIG_SYS_NS16550_SERIAL
|
|
|
|
|
CONFIG_SYS_NUM_CPC
|
|
|
|
|
CONFIG_SYS_NUM_FM1_10GEC
|
|
|
|
|
CONFIG_SYS_NUM_FM1_DTSEC
|
|
|
|
|
CONFIG_SYS_NUM_FM2_10GEC
|
|
|
|
|
CONFIG_SYS_NUM_FM2_DTSEC
|
|
|
|
|
CONFIG_SYS_NUM_FMAN
|
|
|
|
|
CONFIG_SYS_NUM_I2C_BUSES
|
|
|
|
|
CONFIG_SYS_NVRAM_BASE_ADDR
|
|
|
|
|
CONFIG_SYS_NVRAM_SIZE
|
|
|
|
|
CONFIG_SYS_OBIR
|
|
|
|
|
CONFIG_SYS_OMAP_ABE_SYSCK
|
|
|
|
|
CONFIG_SYS_ONENAND_BASE
|
|
|
|
|
CONFIG_SYS_ONENAND_BLOCK_SIZE
|
|
|
|
|
CONFIG_SYS_OSCIN_FREQ
|
|
|
|
|
CONFIG_SYS_OSPR_OFFSET
|
|
|
|
|
CONFIG_SYS_PACNT
|
|
|
|
|
CONFIG_SYS_PADAT
|
|
|
|
|
CONFIG_SYS_PADDR
|
|
|
|
|
CONFIG_SYS_PAGE_SIZE
|
|
|
|
|
CONFIG_SYS_PAMU_ADDR
|
|
|
|
|
CONFIG_SYS_PASPAR
|
|
|
|
|
CONFIG_SYS_PAXE_BASE
|
|
|
|
|
CONFIG_SYS_PAXE_SIZE
|
|
|
|
|
CONFIG_SYS_PBCNT
|
|
|
|
|
CONFIG_SYS_PBDAT
|
|
|
|
|
CONFIG_SYS_PBDDR
|
|
|
|
|
CONFIG_SYS_PBI_FLASH_BASE
|
|
|
|
|
CONFIG_SYS_PBI_FLASH_WINDOW
|
|
|
|
|
CONFIG_SYS_PCCNT
|
|
|
|
|
CONFIG_SYS_PCDAT
|
|
|
|
|
CONFIG_SYS_PCDDR
|
|
|
|
|
CONFIG_SYS_PCI
|
|
|
|
|
CONFIG_SYS_PCI1_ADDR
|
|
|
|
|
CONFIG_SYS_PCI1_IO_BASE
|
|
|
|
|
CONFIG_SYS_PCI1_IO_BUS
|
|
|
|
|
CONFIG_SYS_PCI1_IO_PHYS
|
|
|
|
|
CONFIG_SYS_PCI1_IO_SIZE
|
|
|
|
|
CONFIG_SYS_PCI1_IO_VIRT
|
|
|
|
|
CONFIG_SYS_PCI1_MEM_BASE
|
|
|
|
|
CONFIG_SYS_PCI1_MEM_BUS
|
|
|
|
|
CONFIG_SYS_PCI1_MEM_PHYS
|
|
|
|
|
CONFIG_SYS_PCI1_MEM_SIZE
|
|
|
|
|
CONFIG_SYS_PCI1_MEM_VIRT
|
|
|
|
|
CONFIG_SYS_PCI2_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE
|
|
|
|
|
CONFIG_SYS_PCIE1_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE1_CFG_BASE
|
|
|
|
|
CONFIG_SYS_PCIE1_CFG_SIZE
|
|
|
|
|
CONFIG_SYS_PCIE1_IO_PHYS
|
|
|
|
|
CONFIG_SYS_PCIE1_IO_VIRT
|
|
|
|
|
CONFIG_SYS_PCIE1_MEM_PHYS
|
|
|
|
|
CONFIG_SYS_PCIE1_MEM_VIRT
|
|
|
|
|
CONFIG_SYS_PCIE1_PHYS_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE1_PHYS_BASE
|
|
|
|
|
CONFIG_SYS_PCIE1_VIRT_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE2_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE2_CFG_BASE
|
|
|
|
|
CONFIG_SYS_PCIE2_CFG_SIZE
|
|
|
|
|
CONFIG_SYS_PCIE2_IO_PHYS
|
|
|
|
|
CONFIG_SYS_PCIE2_IO_VIRT
|
|
|
|
|
CONFIG_SYS_PCIE2_MEM_PHYS
|
|
|
|
|
CONFIG_SYS_PCIE2_MEM_VIRT
|
|
|
|
|
CONFIG_SYS_PCIE2_PHYS_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE2_PHYS_BASE
|
|
|
|
|
CONFIG_SYS_PCIE2_VIRT_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE3_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE3_IO_PHYS
|
|
|
|
|
CONFIG_SYS_PCIE3_IO_VIRT
|
|
|
|
|
CONFIG_SYS_PCIE3_MEM_PHYS
|
|
|
|
|
CONFIG_SYS_PCIE3_MEM_VIRT
|
|
|
|
|
CONFIG_SYS_PCIE3_PHYS_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE3_PHYS_SIZE
|
|
|
|
|
CONFIG_SYS_PCIE4_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE4_IO_PHYS
|
|
|
|
|
CONFIG_SYS_PCIE4_IO_VIRT
|
|
|
|
|
CONFIG_SYS_PCIE4_MEM_BUS
|
|
|
|
|
CONFIG_SYS_PCIE4_MEM_PHYS
|
|
|
|
|
CONFIG_SYS_PCIE4_MEM_VIRT
|
|
|
|
|
CONFIG_SYS_PCIE4_PHYS_ADDR
|
|
|
|
|
CONFIG_SYS_PCIE_MMAP_SIZE
|
|
|
|
|
CONFIG_SYS_PDCNT
|
|
|
|
|
CONFIG_SYS_PEHLPAR
|
|
|
|
|
CONFIG_SYS_PIOC_PDR_VAL
|
|
|
|
|
CONFIG_SYS_PIOC_PDR_VAL1
|
|
|
|
|
CONFIG_SYS_PIOC_PPUDR_VAL
|
|
|
|
|
CONFIG_SYS_PIOD_PDR_VAL1
|
|
|
|
|
CONFIG_SYS_PIOD_PPUDR_VAL
|
|
|
|
|
CONFIG_SYS_PJPAR
|
|
|
|
|
CONFIG_SYS_PL310_BASE
|
|
|
|
|
CONFIG_SYS_PLLAR_VAL
|
|
|
|
|
CONFIG_SYS_PLLCR
|
|
|
|
|
CONFIG_SYS_PLL_BYPASS
|
|
|
|
|
CONFIG_SYS_PLL_FDR
|
|
|
|
|
CONFIG_SYS_PLL_ODR
|
|
|
|
|
CONFIG_SYS_PLL_SETTLING_TIME
|
|
|
|
|
CONFIG_SYS_PMAN
|
|
|
|
|
CONFIG_SYS_PME_CLK
|
|
|
|
|
CONFIG_SYS_POST_MEMORY
|
|
|
|
|
CONFIG_SYS_POST_MEM_REGIONS
|
|
|
|
|
CONFIG_SYS_PUAPAR
|
|
|
|
|
CONFIG_SYS_QMAN_CENA_BASE
|
|
|
|
|
CONFIG_SYS_QMAN_CENA_SIZE
|
|
|
|
|
CONFIG_SYS_QMAN_CINH_BASE
|
|
|
|
|
CONFIG_SYS_QMAN_CINH_SIZE
|
|
|
|
|
CONFIG_SYS_QMAN_MEM_BASE
|
|
|
|
|
CONFIG_SYS_QMAN_MEM_PHYS
|
|
|
|
|
CONFIG_SYS_QMAN_MEM_SIZE
|
|
|
|
|
CONFIG_SYS_QMAN_NUM_PORTALS
|
|
|
|
|
CONFIG_SYS_QMAN_SP_CENA_SIZE
|
|
|
|
|
CONFIG_SYS_QMAN_SP_CINH_SIZE
|
|
|
|
|
CONFIG_SYS_QMAN_SWP_ISDR_REG
|
|
|
|
|
CONFIG_SYS_QRIO_BASE
|
|
|
|
|
CONFIG_SYS_QRIO_BASE_PHYS
|
|
|
|
|
CONFIG_SYS_RCAR_I2C0_BASE
|
|
|
|
|
CONFIG_SYS_RCAR_I2C1_BASE
|
|
|
|
|
CONFIG_SYS_RCAR_I2C2_BASE
|
|
|
|
|
CONFIG_SYS_RCAR_I2C3_BASE
|
|
|
|
|
CONFIG_SYS_RFD
|
|
|
|
|
CONFIG_SYS_RGMII1_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_RGMII2_PHY_ADDR
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|
|
|
|
CONFIG_SYS_ROM_BASE
|
|
|
|
|
CONFIG_SYS_RSTC_RMR_VAL
|
|
|
|
|
CONFIG_SYS_RTC_BUS_NUM
|
|
|
|
|
CONFIG_SYS_RTC_CNT
|
|
|
|
|
CONFIG_SYS_RTC_SETUP
|
|
|
|
|
CONFIG_SYS_SATA
|
|
|
|
|
CONFIG_SYS_SATA_FAT_BOOT_PARTITION
|
|
|
|
|
CONFIG_SYS_SBFHDR_DATA_OFFSET
|
|
|
|
|
CONFIG_SYS_SBFHDR_SIZE
|
|
|
|
|
CONFIG_SYS_SCCR_SATACM
|
|
|
|
|
CONFIG_SYS_SCCR_TSEC1CM
|
|
|
|
|
CONFIG_SYS_SCCR_TSEC2CM
|
|
|
|
|
CONFIG_SYS_SCCR_USBDRCM
|
|
|
|
|
CONFIG_SYS_SCR
|
|
|
|
|
CONFIG_SYS_SDRAM
|
|
|
|
|
CONFIG_SYS_SDRAM_BASE
|
|
|
|
|
CONFIG_SYS_SDRAM_BASE0
|
|
|
|
|
CONFIG_SYS_SDRAM_BASE1
|
|
|
|
|
CONFIG_SYS_SDRAM_BASE2
|
|
|
|
|
CONFIG_SYS_SDRAM_CFG1
|
|
|
|
|
CONFIG_SYS_SDRAM_CFG2
|
|
|
|
|
CONFIG_SYS_SDRAM_CTRL
|
|
|
|
|
CONFIG_SYS_SDRAM_EMOD
|
|
|
|
|
CONFIG_SYS_SDRAM_MODE
|
|
|
|
|
CONFIG_SYS_SDRAM_SIZE
|
|
|
|
|
CONFIG_SYS_SDRAM_SIZE0
|
|
|
|
|
CONFIG_SYS_SDRAM_SIZE_LAW
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL1
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL10
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL11
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL12
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL2
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL3
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL4
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL5
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL6
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL7
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL8
|
|
|
|
|
CONFIG_SYS_SDRAM_VAL9
|
|
|
|
|
CONFIG_SYS_SDRC_CR_VAL
|
|
|
|
|
CONFIG_SYS_SDRC_MDR_VAL
|
|
|
|
|
CONFIG_SYS_SDRC_MR_VAL
|
|
|
|
|
CONFIG_SYS_SDRC_MR_VAL1
|
|
|
|
|
CONFIG_SYS_SDRC_MR_VAL2
|
|
|
|
|
CONFIG_SYS_SDRC_MR_VAL3
|
|
|
|
|
CONFIG_SYS_SDRC_MR_VAL4
|
|
|
|
|
CONFIG_SYS_SDRC_MR_VAL5
|
|
|
|
|
CONFIG_SYS_SDRC_TR_VAL
|
|
|
|
|
CONFIG_SYS_SDRC_TR_VAL1
|
|
|
|
|
CONFIG_SYS_SDRC_TR_VAL2
|
|
|
|
|
CONFIG_SYS_SEC_MON_ADDR
|
|
|
|
|
CONFIG_SYS_SEC_MON_OFFSET
|
|
|
|
|
CONFIG_SYS_SERIAL0
|
|
|
|
|
CONFIG_SYS_SERIAL1
|
|
|
|
|
CONFIG_SYS_SERIAL2
|
|
|
|
|
CONFIG_SYS_SERIAL3
|
|
|
|
|
CONFIG_SYS_SFP_ADDR
|
|
|
|
|
CONFIG_SYS_SFP_OFFSET
|
|
|
|
|
CONFIG_SYS_SGMII1_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_SGMII2_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_SGMII3_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_SGMII_LINERATE_MHZ
|
|
|
|
|
CONFIG_SYS_SGMII_RATESCALE
|
|
|
|
|
CONFIG_SYS_SGMII_REFCLK_MHZ
|
|
|
|
|
CONFIG_SYS_SH_SDHI0_BASE
|
|
|
|
|
CONFIG_SYS_SH_SDHI1_BASE
|
|
|
|
|
CONFIG_SYS_SH_SDHI2_BASE
|
|
|
|
|
CONFIG_SYS_SH_SDHI3_BASE
|
|
|
|
|
CONFIG_SYS_SH_SDHI_NR_CHANNEL
|
|
|
|
|
CONFIG_SYS_SICRH
|
|
|
|
|
CONFIG_SYS_SICRL
|
|
|
|
|
CONFIG_SYS_SMC0_CYCLE0_VAL
|
|
|
|
|
CONFIG_SYS_SMC0_MODE0_VAL
|
|
|
|
|
CONFIG_SYS_SMC0_PULSE0_VAL
|
|
|
|
|
CONFIG_SYS_SMC0_SETUP0_VAL
|
|
|
|
|
CONFIG_SYS_SPI_ARGS_OFFS
|
|
|
|
|
CONFIG_SYS_SPI_ARGS_SIZE
|
|
|
|
|
CONFIG_SYS_SPI_BASE
|
|
|
|
|
CONFIG_SYS_SPI_CLK
|
|
|
|
|
CONFIG_SYS_SPI_FLASH_U_BOOT_DST
|
|
|
|
|
CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS
|
|
|
|
|
CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE
|
|
|
|
|
CONFIG_SYS_SPI_FLASH_U_BOOT_START
|
|
|
|
|
CONFIG_SYS_SPI_KERNEL_OFFS
|
|
|
|
|
CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
|
|
|
|
|
CONFIG_SYS_SPI_U_BOOT_SIZE
|
|
|
|
|
CONFIG_SYS_SPL_MALLOC_START
|
|
|
|
|
CONFIG_SYS_SPR
|
|
|
|
|
CONFIG_SYS_SRIO
|
|
|
|
|
CONFIG_SYS_SRIO1_MEM_PHYS
|
|
|
|
|
CONFIG_SYS_SRIO1_MEM_SIZE
|
|
|
|
|
CONFIG_SYS_SRIO1_MEM_VIRT
|
|
|
|
|
CONFIG_SYS_SRIO2_MEM_PHYS
|
|
|
|
|
CONFIG_SYS_SRIO2_MEM_SIZE
|
|
|
|
|
CONFIG_SYS_SRIO2_MEM_VIRT
|
|
|
|
|
CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR
|
|
|
|
|
CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS
|
|
|
|
|
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR
|
|
|
|
|
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS
|
|
|
|
|
CONFIG_SYS_SST_SECT
|
|
|
|
|
CONFIG_SYS_SST_SECTSZ
|
|
|
|
|
CONFIG_SYS_STACK_SIZE
|
|
|
|
|
CONFIG_SYS_TBIPA_VALUE
|
|
|
|
|
CONFIG_SYS_TCLK
|
|
|
|
|
CONFIG_SYS_TIMERBASE
|
|
|
|
|
CONFIG_SYS_TIMER_BASE
|
|
|
|
|
CONFIG_SYS_TIMER_COUNTER
|
|
|
|
|
CONFIG_SYS_TIMER_COUNTS_DOWN
|
|
|
|
|
CONFIG_SYS_TIMER_RATE
|
|
|
|
|
CONFIG_SYS_TMPVIRT
|
|
|
|
|
CONFIG_SYS_TSEC1_OFFSET
|
|
|
|
|
CONFIG_SYS_TX_ETH_BUFFER
|
|
|
|
|
CONFIG_SYS_UART2_ALT3_GPIO
|
|
|
|
|
CONFIG_SYS_UART_PORT
|
|
|
|
|
CONFIG_SYS_UBOOT_BASE
|
|
|
|
|
CONFIG_SYS_UBOOT_START
|
|
|
|
|
CONFIG_SYS_UEC
|
|
|
|
|
CONFIG_SYS_UEC2_PHY_ADDR
|
|
|
|
|
CONFIG_SYS_USB_OHCI_REGS_BASE
|
|
|
|
|
CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
|
|
|
|
|
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN
|
|
|
|
|
CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT
|
|
|
|
|
CONFIG_SYS_VCXK_BASE
|
|
|
|
|
CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
|
|
|
|
|
CONFIG_SYS_VCXK_DOUBLEBUFFERED
|
|
|
|
|
CONFIG_SYS_VCXK_ENABLE_DDR
|
|
|
|
|
CONFIG_SYS_VCXK_ENABLE_PIN
|
|
|
|
|
CONFIG_SYS_VCXK_ENABLE_PORT
|
|
|
|
|
CONFIG_SYS_VCXK_INVERT_DDR
|
|
|
|
|
CONFIG_SYS_VCXK_INVERT_PIN
|
|
|
|
|
CONFIG_SYS_VCXK_INVERT_PORT
|
|
|
|
|
CONFIG_SYS_VCXK_REQUEST_DDR
|
|
|
|
|
CONFIG_SYS_VCXK_REQUEST_PIN
|
|
|
|
|
CONFIG_SYS_VCXK_REQUEST_PORT
|
|
|
|
|
CONFIG_SYS_VIDEO_LOGO_MAX_SIZE
|
|
|
|
|
CONFIG_SYS_VSC7385_BASE
|
|
|
|
|
CONFIG_SYS_VSC7385_BASE_PHYS
|
|
|
|
|
CONFIG_SYS_VSC7385_BR_PRELIM
|
|
|
|
|
CONFIG_SYS_VSC7385_OR_PRELIM
|
|
|
|
|
CONFIG_SYS_WATCHDOG_VALUE
|
|
|
|
|
CONFIG_SYS_WDTC_WDMR_VAL
|
|
|
|
|
CONFIG_SYS_WRITE_SWAPPED_DATA
|
|
|
|
|
CONFIG_SYS_XHCI_USB1_ADDR
|
|
|
|
|
CONFIG_SYS_XHCI_USB2_ADDR
|
|
|
|
|
CONFIG_SYS_XHCI_USB3_ADDR
|
|
|
|
|
CONFIG_TCA642X
|
|
|
|
|
CONFIG_TEGRA_BOARD_STRING
|
|
|
|
|
CONFIG_TEGRA_CLOCK_SCALING
|
|
|
|
|
CONFIG_TEGRA_ENABLE_UARTA
|
|
|
|
|
CONFIG_TEGRA_ENABLE_UARTD
|
|
|
|
|
CONFIG_TEGRA_LP0
|
|
|
|
|
CONFIG_TEGRA_PMU
|
|
|
|
|
CONFIG_TEGRA_SLINK_CTRLS
|
|
|
|
|
CONFIG_TEGRA_SPI
|
|
|
|
|
CONFIG_TEGRA_UARTA_GPU
|
|
|
|
|
CONFIG_TEGRA_UARTA_SDIO1
|
|
|
|
|
CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
|
|
|
|
|
CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
|
|
|
|
|
CONFIG_TESTPIN_MASK
|
|
|
|
|
CONFIG_TESTPIN_REG
|
|
|
|
|
CONFIG_THOR_RESET_OFF
|
|
|
|
|
CONFIG_TMU_TIMER
|
|
|
|
|
CONFIG_TPM_TIS_BASE_ADDRESS
|
|
|
|
|
CONFIG_TPS6586X_POWER
|
|
|
|
|
CONFIG_TSEC
|
|
|
|
|
CONFIG_TSEC1
|
|
|
|
|
CONFIG_TSEC1_NAME
|
|
|
|
|
CONFIG_TSEC2
|
|
|
|
|
CONFIG_TSEC2_NAME
|
|
|
|
|
CONFIG_TSEC3
|
|
|
|
|
CONFIG_TSEC3_NAME
|
|
|
|
|
CONFIG_TSEC4
|
|
|
|
|
CONFIG_TSEC4_NAME
|
|
|
|
|
CONFIG_TSECV2
|
|
|
|
|
CONFIG_TSECV2_1
|
|
|
|
|
CONFIG_TSEC_TBICR_SETTINGS
|
|
|
|
|
CONFIG_TWL6030_POWER
|
|
|
|
|
CONFIG_UBIFS_VOLUME
|
|
|
|
|
CONFIG_UBI_PART
|
|
|
|
|
CONFIG_UBI_SIZE
|
|
|
|
|
CONFIG_UBOOTPATH
|
|
|
|
|
CONFIG_UBOOT_SECTOR_COUNT
|
|
|
|
|
CONFIG_UBOOT_SECTOR_START
|
|
|
|
|
CONFIG_UEC_ETH
|
|
|
|
|
CONFIG_UEC_ETH2
|
|
|
|
|
CONFIG_USART_BASE
|
|
|
|
|
CONFIG_USART_ID
|
|
|
|
|
CONFIG_USBD_HS
|
|
|
|
|
CONFIG_USBD_MANUFACTURER
|
|
|
|
|
CONFIG_USBD_PRODUCTID_CDCACM
|
|
|
|
|
CONFIG_USBD_PRODUCTID_GSERIAL
|
|
|
|
|
CONFIG_USBD_PRODUCT_NAME
|
|
|
|
|
CONFIG_USBD_VENDORID
|
|
|
|
|
CONFIG_USBNET_DEV_ADDR
|
|
|
|
|
CONFIG_USB_BOOTING
|
|
|
|
|
CONFIG_USB_DEVICE
|
|
|
|
|
CONFIG_USB_EXT2_BOOT
|
|
|
|
|
CONFIG_USB_FAT_BOOT
|
|
|
|
|
CONFIG_USB_GADGET_AT91
|
|
|
|
|
CONFIG_USB_ISP1301_I2C_ADDR
|
|
|
|
|
CONFIG_USB_TTY
|
|
|
|
|
CONFIG_U_BOOT_HDR_SIZE
|
|
|
|
|
CONFIG_VAR_SIZE_SPL
|
|
|
|
|
CONFIG_VERY_BIG_RAM
|
|
|
|
|
CONFIG_VSC7385_ENET
|
|
|
|
|
CONFIG_VSC7385_IMAGE
|
|
|
|
|
CONFIG_VSC7385_IMAGE_SIZE
|
|
|
|
|
CONFIG_VSC9953
|
|
|
|
|
CONFIG_WATCHDOG_PRESC
|
|
|
|
|
CONFIG_WATCHDOG_RC
|
|
|
|
|
CONFIG_WATCHDOG_TIMEOUT
|
|
|
|
|
CONFIG_X86EMU_RAW_IO
|
|
|
|
|
CONFIG_X86_MRC_ADDR
|
|
|
|
|
CONFIG_X86_REFCODE_ADDR
|
|
|
|
|
CONFIG_X86_REFCODE_RUN_ADDR
|
