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61 lines
1.9 KiB
Text
61 lines
1.9 KiB
Text
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ST DWC3 glue logic
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This file documents the parameters for the dwc3-st driver.
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This driver controls the glue logic used to configure the dwc3 core on
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STiH407 based platforms.
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Required properties:
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- compatible : must be "st,stih407-dwc3"
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- reg : glue logic base address and USB syscfg ctrl register offset
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- reg-names : should be "reg-glue" and "syscfg-reg"
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- st,syscon : should be phandle to system configuration node which
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encompasses the glue registers
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- resets : list of phandle and reset specifier pairs. There should be two entries, one
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for the powerdown and softreset lines of the usb3 IP
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- reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
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- #address-cells, #size-cells : should be '1' if the device has sub-nodes
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with 'reg' property
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- pinctl-names : A pinctrl state named "default" must be defined
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- pinctrl-0 : Pin control group
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- ranges : allows valid 1:1 translation between child's address space and
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parent's address space
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Sub-nodes:
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The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
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example below.
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NB: The dr_mode property is NOT optional for this driver, as the default value
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is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are
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either "host" or "device".
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Example:
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st_dwc3: dwc3@8f94000 {
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status = "disabled";
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compatible = "st,stih407-dwc3";
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reg = <0x08f94000 0x1000>, <0x110 0x4>;
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reg-names = "reg-glue", "syscfg-reg";
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st,syscfg = <&syscfg_core>;
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resets = <&powerdown STIH407_USB3_POWERDOWN>,
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<&softreset STIH407_MIPHY2_SOFTRESET>;
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reset-names = "powerdown", "softreset";
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#address-cells = <1>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb3>;
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ranges;
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dwc3: dwc3@9900000 {
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compatible = "snps,dwc3";
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reg = <0x09900000 0x100000>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
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dr_mode = "host";
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phy-names = "usb2-phy", "usb3-phy";
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phys = <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>;
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};
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};
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