2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_RISCV=y
|
|
|
|
CONFIG_SYS_MALLOC_LEN=0x800000
|
|
|
|
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
|
|
|
CONFIG_SPL_GPIO=y
|
|
|
|
CONFIG_NR_DRAM_BANKS=1
|
|
|
|
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
|
|
|
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000000
|
2023-05-01 15:50:26 +00:00
|
|
|
CONFIG_SF_DEFAULT_SPEED=100000000
|
2023-08-08 13:14:36 +00:00
|
|
|
CONFIG_ENV_SIZE=0x10000
|
|
|
|
CONFIG_ENV_OFFSET=0xf0000
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_SPL_DM_SPI=y
|
2023-06-15 09:36:45 +00:00
|
|
|
CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_SPL_TEXT_BASE=0x8000000
|
2023-05-01 15:50:26 +00:00
|
|
|
CONFIG_OF_LIBFDT_OVERLAY=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_DM_RESET=y
|
|
|
|
CONFIG_SPL_MMC=y
|
2023-06-15 09:36:50 +00:00
|
|
|
CONFIG_SPL_DRIVERS_MISC=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_SPL_STACK=0x8180000
|
|
|
|
CONFIG_SPL=y
|
|
|
|
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|
|
|
CONFIG_SPL_SPI=y
|
|
|
|
CONFIG_SYS_LOAD_ADDR=0x82000000
|
2023-07-25 09:46:49 +00:00
|
|
|
CONFIG_SYS_PCI_64BIT=y
|
|
|
|
CONFIG_PCI=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
|
|
|
|
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000
|
|
|
|
CONFIG_ARCH_RV64I=y
|
|
|
|
CONFIG_CMODEL_MEDANY=y
|
|
|
|
CONFIG_RISCV_SMODE=y
|
2023-06-15 09:36:50 +00:00
|
|
|
# CONFIG_OF_BOARD_FIXUP is not set
|
2023-10-02 14:35:27 +00:00
|
|
|
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_FIT=y
|
2024-01-03 14:26:16 +00:00
|
|
|
CONFIG_SYS_BOOTM_LEN=0x4000000
|
2023-05-01 15:50:26 +00:00
|
|
|
CONFIG_DISTRO_DEFAULTS=y
|
configs: visionfive2: enable bootstage configs
Enable BOOTSTAGE configuration and its command for visionfive2 board.
The feature can be useful for analyzing the elapsed time between boot
stages.
TODO: define / reserve memory region for boot stage stash
StarFive # bootstage report
Timer summary in microseconds (10 records):
Mark Elapsed Stage
0 0 reset
3,139,338 3,139,338 board_init_f
3,176,753 37,415 board_init_r
4,036,111 859,358 eth_common_init
4,101,599 65,488 eth_initialize
4,105,799 4,200 main_loop
4,145,207 39,408 usb_start
5,440,963 1,295,756 cli_loop
Accumulated time:
10,093 dm_f
15,867 dm_r
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-10 08:49:18 +00:00
|
|
|
CONFIG_BOOTSTAGE=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_QSPI_BOOT=y
|
|
|
|
CONFIG_SD_BOOT=y
|
2023-10-02 17:58:20 +00:00
|
|
|
CONFIG_OF_BOARD_SETUP=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_USE_BOOTARGS=y
|
|
|
|
CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
|
|
|
|
CONFIG_USE_PREBOOT=y
|
2023-08-22 14:33:56 +00:00
|
|
|
CONFIG_PREBOOT="nvme scan; usb start; setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};"
|
2023-06-15 09:36:45 +00:00
|
|
|
CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
|
2024-01-03 14:26:16 +00:00
|
|
|
CONFIG_SYS_CBSIZE=256
|
|
|
|
CONFIG_SYS_PBSIZE=276
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_DISPLAY_CPUINFO=y
|
|
|
|
CONFIG_DISPLAY_BOARDINFO=y
|
2023-06-15 09:36:50 +00:00
|
|
|
CONFIG_ID_EEPROM=y
|
|
|
|
CONFIG_SYS_EEPROM_BUS_NUM=5
|
2023-10-02 14:35:27 +00:00
|
|
|
CONFIG_PCI_INIT_R=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_SPL_MAX_SIZE=0x40000
|
|
|
|
CONFIG_SPL_PAD_TO=0x0
|
|
|
|
CONFIG_SPL_BSS_START_ADDR=0x8040000
|
|
|
|
CONFIG_SPL_BSS_MAX_SIZE=0x10000
|
|
|
|
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
2023-09-26 14:14:16 +00:00
|
|
|
CONFIG_SPL_SYS_MALLOC=y
|
|
|
|
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
|
|
|
|
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
|
|
|
|
CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
|
|
|
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
|
2023-06-15 09:36:50 +00:00
|
|
|
CONFIG_SPL_I2C=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_SPL_DM_SPI_FLASH=y
|
|
|
|
CONFIG_SPL_DM_RESET=y
|
|
|
|
CONFIG_SPL_SPI_LOAD=y
|
2023-10-02 14:35:27 +00:00
|
|
|
CONFIG_SYS_PROMPT="StarFive # "
|
2023-06-15 09:36:50 +00:00
|
|
|
CONFIG_CMD_EEPROM=y
|
|
|
|
CONFIG_SYS_EEPROM_SIZE=512
|
|
|
|
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
|
|
|
|
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_CMD_MEMINFO=y
|
2023-06-15 09:36:50 +00:00
|
|
|
CONFIG_CMD_I2C=y
|
2023-07-25 09:46:49 +00:00
|
|
|
CONFIG_CMD_PCI=y
|
2023-08-07 08:53:38 +00:00
|
|
|
CONFIG_CMD_USB=y
|
2023-11-05 23:13:18 +00:00
|
|
|
CONFIG_CMD_WDT=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_CMD_TFTPPUT=y
|
configs: visionfive2: enable bootstage configs
Enable BOOTSTAGE configuration and its command for visionfive2 board.
The feature can be useful for analyzing the elapsed time between boot
stages.
TODO: define / reserve memory region for boot stage stash
StarFive # bootstage report
Timer summary in microseconds (10 records):
Mark Elapsed Stage
0 0 reset
3,139,338 3,139,338 board_init_f
3,176,753 37,415 board_init_r
4,036,111 859,358 eth_common_init
4,101,599 65,488 eth_initialize
4,105,799 4,200 main_loop
4,145,207 39,408 usb_start
5,440,963 1,295,756 cli_loop
Accumulated time:
10,093 dm_f
15,867 dm_r
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-10-10 08:49:18 +00:00
|
|
|
CONFIG_CMD_BOOTSTAGE=y
|
2023-06-15 09:36:50 +00:00
|
|
|
CONFIG_OF_BOARD=y
|
2023-10-02 14:35:27 +00:00
|
|
|
CONFIG_ENV_OVERWRITE=y
|
|
|
|
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|
|
|
CONFIG_ENV_SECT_SIZE_AUTO=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
2023-06-15 09:36:50 +00:00
|
|
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
2023-06-15 09:36:47 +00:00
|
|
|
CONFIG_REGMAP=y
|
|
|
|
CONFIG_SYSCON=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_SPL_CLK_COMPOSITE_CCF=y
|
|
|
|
CONFIG_CLK_COMPOSITE_CCF=y
|
|
|
|
CONFIG_SPL_CLK_JH7110=y
|
2023-06-15 09:36:50 +00:00
|
|
|
CONFIG_DM_I2C=y
|
|
|
|
CONFIG_SYS_I2C_DW=y
|
|
|
|
CONFIG_MISC=y
|
|
|
|
CONFIG_I2C_EEPROM=y
|
|
|
|
CONFIG_SPL_I2C_EEPROM=y
|
|
|
|
CONFIG_SYS_I2C_EEPROM_ADDR=0X50
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_MMC_HS400_SUPPORT=y
|
|
|
|
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
|
|
|
CONFIG_MMC_DW=y
|
|
|
|
CONFIG_MMC_DW_SNPS=y
|
|
|
|
CONFIG_SPI_FLASH_EON=y
|
|
|
|
CONFIG_SPI_FLASH_GIGADEVICE=y
|
|
|
|
CONFIG_SPI_FLASH_ISSI=y
|
|
|
|
CONFIG_SPI_FLASH_MACRONIX=y
|
2023-06-15 09:36:47 +00:00
|
|
|
CONFIG_PHY_MOTORCOMM=y
|
|
|
|
CONFIG_DM_MDIO=y
|
|
|
|
CONFIG_DM_ETH_PHY=y
|
|
|
|
CONFIG_DWC_ETH_QOS=y
|
|
|
|
CONFIG_DWC_ETH_QOS_STARFIVE=y
|
|
|
|
CONFIG_RGMII=y
|
|
|
|
CONFIG_RMII=y
|
2023-07-20 11:37:29 +00:00
|
|
|
CONFIG_RTL8169=y
|
2023-07-25 09:46:49 +00:00
|
|
|
CONFIG_NVME_PCI=y
|
|
|
|
CONFIG_DM_PCI_COMPAT=y
|
|
|
|
CONFIG_PCI_REGION_MULTI_ENTRY=y
|
|
|
|
CONFIG_PCIE_STARFIVE_JH7110=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_PINCTRL=y
|
|
|
|
CONFIG_PINCONF=y
|
|
|
|
CONFIG_SPL_PINCTRL=y
|
|
|
|
CONFIG_SPL_PINCONF=y
|
|
|
|
CONFIG_SPL_PINCTRL_STARFIVE=y
|
|
|
|
CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
|
|
|
|
CONFIG_PINCTRL_STARFIVE=y
|
|
|
|
# CONFIG_RAM_SIFIVE is not set
|
2023-11-01 12:16:52 +00:00
|
|
|
CONFIG_DM_RNG=y
|
|
|
|
CONFIG_RNG_JH7110=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_SYS_NS16550=y
|
|
|
|
CONFIG_CADENCE_QSPI=y
|
2023-10-31 08:24:39 +00:00
|
|
|
CONFIG_SYSRESET=y
|
2023-03-16 02:53:32 +00:00
|
|
|
CONFIG_TIMER_EARLY=y
|
2023-08-07 08:53:38 +00:00
|
|
|
CONFIG_USB=y
|
|
|
|
CONFIG_USB_XHCI_HCD=y
|
|
|
|
CONFIG_USB_XHCI_PCI=y
|
2023-08-22 14:33:56 +00:00
|
|
|
CONFIG_USB_EHCI_HCD=y
|
|
|
|
CONFIG_USB_EHCI_PCI=y
|
|
|
|
CONFIG_USB_OHCI_HCD=y
|
|
|
|
CONFIG_USB_OHCI_PCI=y
|
2023-08-07 08:53:38 +00:00
|
|
|
CONFIG_USB_KEYBOARD=y
|
2023-11-05 23:13:18 +00:00
|
|
|
# CONFIG_WATCHDOG is not set
|
|
|
|
# CONFIG_WATCHDOG_AUTOSTART is not set
|
|
|
|
CONFIG_WDT=y
|
|
|
|
CONFIG_WDT_STARFIVE=y
|