2019-12-09 13:43:03 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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2020-05-10 17:40:02 +00:00
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#include <init.h>
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2020-10-31 03:38:53 +00:00
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#include <asm/global_data.h>
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2019-12-09 13:43:03 +00:00
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mx7ulp-pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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2021-08-25 15:47:18 +00:00
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#ifdef CONFIG_OPTEE_TZDRAM_SIZE
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gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
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#endif
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2019-12-09 13:43:03 +00:00
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return 0;
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}
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static iomux_cfg_t const lpuart4_pads[] = {
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MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
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ARRAY_SIZE(lpuart4_pads));
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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2021-09-12 14:32:57 +00:00
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#ifdef CONFIG_SPL_BUILD
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#include <spl.h>
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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if (!strcmp(name, "imx7ulp-com"))
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return 0;
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return -1;
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}
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#endif
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void spl_board_init(void)
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{
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preloader_console_init();
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}
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void board_init_f(ulong dummy)
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{
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arch_cpu_init();
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board_early_init_f();
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}
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#endif
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