2009-06-14 22:21:28 +00:00
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/*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* Eric Schumann, Phytec Messtechnik
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* adapted for mt46v32m16-75 DDR-RAM
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2009-06-14 22:21:28 +00:00
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*/
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#define SDRAM_DDR 1 /* is DDR */
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/* Settings for XLB = 132 MHz */
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x71500F00
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#define SDRAM_CONFIG1 0x73711930
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#define SDRAM_CONFIG2 0x47770000
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#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */
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