u-boot/include/440_i2c.h

#ifndef _440_i2c_h_
#define _440_i2c_h_

#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
#else
#define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
#endif /*CONFIG_440EP CONFIG_440GR*/

#define	   I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
#define    IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
#define    IIC_SDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
#define    IIC_LMADR	(I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
#define    IIC_HMADR	(I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
#define    IIC_CNTL	(I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
#define    IIC_MDCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
#define    IIC_STS	(I2C_REGISTERS_BASE_ADDRESS+IICSTS)
#define    IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
#define    IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
#define    IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
#define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
#define    IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
#define    IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
#define    IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
#define    IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)

/* MDCNTL Register Bit definition */
#define    IIC_MDCNTL_HSCL 0x01
#define    IIC_MDCNTL_EUBS 0x02
#define    IIC_MDCNTL_EINT 0x04
#define    IIC_MDCNTL_ESM  0x08
#define    IIC_MDCNTL_FSM  0x10
#define    IIC_MDCNTL_EGC  0x20
#define    IIC_MDCNTL_FMDB 0x40
#define    IIC_MDCNTL_FSDB 0x80

/* CNTL Register Bit definition */
#define    IIC_CNTL_PT     0x01
#define    IIC_CNTL_READ   0x02
#define    IIC_CNTL_CHT    0x04
#define    IIC_CNTL_RPST   0x08
/* bit 2/3 for Transfer count*/
#define    IIC_CNTL_AMD    0x40
#define    IIC_CNTL_HMT    0x80

/* STS Register Bit definition */
#define    IIC_STS_PT	   0X01
#define    IIC_STS_IRQA    0x02
#define    IIC_STS_ERR	   0X04
#define    IIC_STS_SCMP    0x08
#define    IIC_STS_MDBF    0x10
#define    IIC_STS_MDBS    0X20
#define    IIC_STS_SLPR    0x40
#define    IIC_STS_SSS     0x80

/* EXTSTS Register Bit definition */
#define    IIC_EXTSTS_XFRA 0X01
#define    IIC_EXTSTS_ICT  0X02
#define    IIC_EXTSTS_LA   0X04

/* XTCNTLSS Register Bit definition */
#define    IIC_XTCNTLSS_SRST  0x01
#define    IIC_XTCNTLSS_EPI   0x02
#define    IIC_XTCNTLSS_SDBF  0x04
#define    IIC_XTCNTLSS_SBDD  0x08
#define    IIC_XTCNTLSS_SWS   0x10
#define    IIC_XTCNTLSS_SWC   0x20
#define    IIC_XTCNTLSS_SRS   0x40
#define    IIC_XTCNTLSS_SRC   0x80
#endif
Initial revision 2002-08-06 20:46:37 +00:00			`#ifndef _440_i2c_h_`
			`#define _440_i2c_h_`

Add support for AMCC Sequoia PPC440EPx eval board - Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006 2006-09-07 09:51:23 +00:00			`#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \`
			`defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)`
Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone. Patch by Steven Blakeslee, 27 Jul 2005 2005-08-01 14:41:48 +00:00			`#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)`
			`#else`
Initial revision 2002-08-06 20:46:37 +00:00			`#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)`
Changed CONFIG_440_xx to CONFIG_440xx for a consistent design (405 and linux) Patch by Stefan Roese, 08 Aug 2005 2005-08-08 10:42:22 +00:00			`#endif /CONFIG_440EP CONFIG_440GR/`
Initial revision 2002-08-06 20:46:37 +00:00
			`#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR`
			`#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)`
			`#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)`
			`#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)`
			`#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)`
			`#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)`
			`#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)`
			`#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)`
			`#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)`
			`#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)`
			`#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)`
			`#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)`
			`#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)`
			`#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)`
			`#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)`
			`#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)`

			`/* MDCNTL Register Bit definition */`
			`#define IIC_MDCNTL_HSCL 0x01`
			`#define IIC_MDCNTL_EUBS 0x02`
			`#define IIC_MDCNTL_EINT 0x04`
			`#define IIC_MDCNTL_ESM 0x08`
			`#define IIC_MDCNTL_FSM 0x10`
			`#define IIC_MDCNTL_EGC 0x20`
			`#define IIC_MDCNTL_FMDB 0x40`
			`#define IIC_MDCNTL_FSDB 0x80`

			`/* CNTL Register Bit definition */`
			`#define IIC_CNTL_PT 0x01`
			`#define IIC_CNTL_READ 0x02`
			`#define IIC_CNTL_CHT 0x04`
			`#define IIC_CNTL_RPST 0x08`
			`/* bit 2/3 for Transfer count*/`
			`#define IIC_CNTL_AMD 0x40`
			`#define IIC_CNTL_HMT 0x80`

			`/* STS Register Bit definition */`
			`#define IIC_STS_PT 0X01`
			`#define IIC_STS_IRQA 0x02`
			`#define IIC_STS_ERR 0X04`
			`#define IIC_STS_SCMP 0x08`
			`#define IIC_STS_MDBF 0x10`
			`#define IIC_STS_MDBS 0X20`
			`#define IIC_STS_SLPR 0x40`
			`#define IIC_STS_SSS 0x80`

			`/* EXTSTS Register Bit definition */`
			`#define IIC_EXTSTS_XFRA 0X01`
			`#define IIC_EXTSTS_ICT 0X02`
			`#define IIC_EXTSTS_LA 0X04`

			`/* XTCNTLSS Register Bit definition */`
			`#define IIC_XTCNTLSS_SRST 0x01`
			`#define IIC_XTCNTLSS_EPI 0x02`
			`#define IIC_XTCNTLSS_SDBF 0x04`
			`#define IIC_XTCNTLSS_SBDD 0x08`
			`#define IIC_XTCNTLSS_SWS 0x10`
			`#define IIC_XTCNTLSS_SWC 0x20`
			`#define IIC_XTCNTLSS_SRS 0x40`
			`#define IIC_XTCNTLSS_SRC 0x80`
			`#endif`