2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2015-07-21 22:48:40 +00:00
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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* Fabio Estevam <fabio.estevam@freescale.com>
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*/
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#ifndef __MAX77696_PMIC_H__
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#define __MAX77696_PMIC_H__
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#define CONFIG_POWER_MAX77696_I2C_ADDR 0x3C
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enum {
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L01_CNFG1 = 0x43,
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L01_CNFG2,
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L02_CNFG1,
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L02_CNFG2,
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L03_CNFG1,
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L03_CNFG2,
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L04_CNFG1,
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L04_CNFG2,
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L05_CNFG1,
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L05_CNFG2,
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L06_CNFG1,
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L06_CNFG2,
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L07_CNFG1,
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L07_CNFG2,
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L08_CNFG1,
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L08_CNFG2,
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L09_CNFG1,
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L09_CNFG2,
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L10_CNFG1,
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L10_CNFG2,
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LDO_INT1,
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LDO_INT2,
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LDO_INT1M,
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LDO_INT2M,
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LDO_CNFG3,
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SW1_CNTRL,
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SW2_CNTRL,
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SW3_CNTRL,
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SW4_CNTRL,
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EPDCNFG,
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EPDINTS,
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EPDINT,
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EPDINTM,
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EPDVCOM,
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EPDVEE,
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EPDVNEG,
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EPDVPOS,
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EPDVDDH,
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EPDSEQ,
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EPDOKINTS,
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CID = 0x9c,
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PMIC_NUM_OF_REGS,
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};
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int power_max77696_init(unsigned char bus);
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#endif
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