2018-08-27 10:27:08 +00:00
|
|
|
if ARCH_K3
|
|
|
|
|
|
|
|
|
|
choice
|
|
|
|
|
prompt "Texas Instruments' K3 based SoC select"
|
|
|
|
|
optional
|
|
|
|
|
|
2018-08-27 10:27:09 +00:00
|
|
|
config SOC_K3_AM6
|
|
|
|
|
bool "TI's K3 based AM6 SoC Family Support"
|
|
|
|
|
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
config SOC_K3_J721E
|
|
|
|
|
bool "TI's K3 based J721E SoC Family Support"
|
|
|
|
|
|
2018-08-27 10:27:08 +00:00
|
|
|
endchoice
|
|
|
|
|
|
|
|
|
|
config SYS_SOC
|
|
|
|
|
default "k3"
|
|
|
|
|
|
2018-08-27 10:27:09 +00:00
|
|
|
config SYS_K3_NON_SECURE_MSRAM_SIZE
|
|
|
|
|
hex
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
default 0x80000 if SOC_K3_AM6
|
|
|
|
|
default 0x100000 if SOC_K3_J721E
|
2018-08-27 10:27:09 +00:00
|
|
|
help
|
|
|
|
|
Describes the total size of the MCU MSRAM. This doesn't
|
|
|
|
|
specify the total size of SPL as ROM can use some part
|
|
|
|
|
of this RAM. Once ROM gives control to SPL then this
|
|
|
|
|
complete size can be usable.
|
|
|
|
|
|
|
|
|
|
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
|
|
|
|
|
hex
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
default 0x58000 if SOC_K3_AM6
|
|
|
|
|
default 0xc0000 if SOC_K3_J721E
|
2018-08-27 10:27:09 +00:00
|
|
|
help
|
|
|
|
|
Describes the maximum size of the image that ROM can download
|
|
|
|
|
from any boot media.
|
|
|
|
|
|
|
|
|
|
config SYS_K3_MCU_SCRATCHPAD_BASE
|
|
|
|
|
hex
|
|
|
|
|
default 0x40280000 if SOC_K3_AM6
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
default 0x40280000 if SOC_K3_J721E
|
2018-08-27 10:27:09 +00:00
|
|
|
help
|
|
|
|
|
Describes the base address of MCU Scratchpad RAM.
|
|
|
|
|
|
|
|
|
|
config SYS_K3_MCU_SCRATCHPAD_SIZE
|
|
|
|
|
hex
|
|
|
|
|
default 0x200 if SOC_K3_AM6
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
default 0x200 if SOC_K3_J721E
|
2018-08-27 10:27:09 +00:00
|
|
|
help
|
|
|
|
|
Describes the size of MCU Scratchpad RAM.
|
|
|
|
|
|
2018-08-27 10:27:11 +00:00
|
|
|
config SYS_K3_BOOT_PARAM_TABLE_INDEX
|
|
|
|
|
hex
|
|
|
|
|
default 0x41c7fbfc if SOC_K3_AM6
|
arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
|
|
|
default 0x41cffc00 if SOC_K3_J721E
|
2018-08-27 10:27:11 +00:00
|
|
|
help
|
|
|
|
|
Address at which ROM stores the value which determines if SPL
|
|
|
|
|
is booted up by primary boot media or secondary boot media.
|
|
|
|
|
|
2018-11-02 14:21:04 +00:00
|
|
|
config SYS_K3_KEY
|
|
|
|
|
string "Key used to generate x509 certificate"
|
|
|
|
|
help
|
|
|
|
|
This option enables to provide a custom key that can be used for
|
|
|
|
|
generating x509 certificate for spl binary. If not needed leave
|
|
|
|
|
it blank so that a random key is generated and used.
|
|
|
|
|
|
|
|
|
|
config SYS_K3_BOOT_CORE_ID
|
|
|
|
|
int
|
|
|
|
|
default 16
|
|
|
|
|
|
2019-06-04 22:55:47 +00:00
|
|
|
config K3_LOAD_SYSFW
|
|
|
|
|
bool
|
|
|
|
|
depends on SPL
|
|
|
|
|
|
|
|
|
|
config K3_SYSFW_IMAGE_NAME
|
|
|
|
|
string "File name of SYSFW firmware and configuration blob"
|
|
|
|
|
depends on K3_LOAD_SYSFW
|
|
|
|
|
default "sysfw.itb"
|
|
|
|
|
help
|
|
|
|
|
Filename of the combined System Firmware and configuration image tree
|
|
|
|
|
blob to be loaded when booting from a filesystem.
|
|
|
|
|
|
|
|
|
|
config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
|
|
|
|
|
hex "MMC sector to load SYSFW firmware and configuration blob from"
|
|
|
|
|
depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
|
|
|
|
default 0x3600
|
|
|
|
|
help
|
|
|
|
|
Address on the MMC to load the combined System Firmware and
|
|
|
|
|
configuration image tree blob from, when the MMC is being used
|
|
|
|
|
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
|
|
|
|
|
|
|
|
|
|
config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
|
|
|
|
|
hex "MMC partition to load SYSFW firmware and configuration blob from"
|
|
|
|
|
depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
|
|
|
|
|
default 2
|
|
|
|
|
help
|
|
|
|
|
Partition on the MMC to the combined System Firmware and configuration
|
|
|
|
|
image tree blob from, when the MMC is being used in raw mode.
|
|
|
|
|
|
|
|
|
|
config K3_SYSFW_IMAGE_SIZE_MAX
|
|
|
|
|
int "Amount of memory dynamically allocated for loading SYSFW blob"
|
|
|
|
|
depends on K3_LOAD_SYSFW
|
|
|
|
|
default 269000
|
|
|
|
|
help
|
|
|
|
|
Amount of memory (in bytes) reserved through dynamic allocation at
|
|
|
|
|
runtime for loading the combined System Firmware and configuration image
|
|
|
|
|
tree blob. Keep it as tight as possible, as this directly affects the
|
|
|
|
|
overall SPL memory footprint.
|
|
|
|
|
|
2018-11-02 14:21:05 +00:00
|
|
|
config SYS_K3_SPL_ATF
|
|
|
|
|
bool "Start Cortex-A from SPL"
|
|
|
|
|
depends on SPL && CPU_V7R
|
|
|
|
|
help
|
|
|
|
|
Enabling this will try to start Cortex-A (typically with ATF)
|
|
|
|
|
after SPL from R5.
|
|
|
|
|
|
2018-08-27 10:29:06 +00:00
|
|
|
source "board/ti/am65x/Kconfig"
|
2018-08-27 10:27:08 +00:00
|
|
|
endif
|
