2019-03-05 02:32:35 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2018 NXP
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2023-04-28 04:08:09 +00:00
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#include <firmware/imx/sci/sci.h>
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2019-03-05 02:32:35 +00:00
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#include <asm/arch/clock.h>
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#include <dt-bindings/clock/imx8qm-clock.h>
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#include <dt-bindings/soc/imx_rsrc.h>
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#include <misc.h>
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#include "clk-imx8.h"
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2023-02-05 22:36:26 +00:00
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#if IS_ENABLED(CONFIG_CMD_CLK)
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2019-03-05 02:32:35 +00:00
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struct imx8_clks imx8_clk_names[] = {
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{ IMX8QM_A53_DIV, "A53_DIV" },
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{ IMX8QM_UART0_CLK, "UART0" },
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{ IMX8QM_UART1_CLK, "UART1" },
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{ IMX8QM_UART2_CLK, "UART2" },
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{ IMX8QM_UART3_CLK, "UART3" },
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{ IMX8QM_SDHC0_CLK, "SDHC0" },
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{ IMX8QM_SDHC1_CLK, "SDHC1" },
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{ IMX8QM_SDHC2_CLK, "SDHC2" },
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{ IMX8QM_ENET0_AHB_CLK, "ENET0_AHB" },
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{ IMX8QM_ENET0_IPG_CLK, "ENET0_IPG" },
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{ IMX8QM_ENET0_REF_DIV, "ENET0_REF" },
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{ IMX8QM_ENET0_PTP_CLK, "ENET0_PTP" },
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{ IMX8QM_ENET1_AHB_CLK, "ENET1_AHB" },
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{ IMX8QM_ENET1_IPG_CLK, "ENET1_IPG" },
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{ IMX8QM_ENET1_REF_DIV, "ENET1_REF" },
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{ IMX8QM_ENET1_PTP_CLK, "ENET1_PTP" },
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};
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int num_clks = ARRAY_SIZE(imx8_clk_names);
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#endif
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ulong imx8_clk_get_rate(struct clk *clk)
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{
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sc_pm_clk_t pm_clk;
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ulong rate;
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u16 resource;
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int ret;
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debug("%s(#%lu)\n", __func__, clk->id);
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switch (clk->id) {
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case IMX8QM_A53_DIV:
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resource = SC_R_A53;
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pm_clk = SC_PM_CLK_CPU;
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break;
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C0_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C0_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C0_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C1_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C1_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C1_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C2_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C2_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C2_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C3_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C3_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C3_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_SDHC0_IPG_CLK:
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case IMX8QM_SDHC0_CLK:
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case IMX8QM_SDHC0_DIV:
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resource = SC_R_SDHC_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_SDHC1_IPG_CLK:
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case IMX8QM_SDHC1_CLK:
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case IMX8QM_SDHC1_DIV:
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resource = SC_R_SDHC_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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2019-05-31 16:00:17 +00:00
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case IMX8QM_SDHC2_IPG_CLK:
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case IMX8QM_SDHC2_CLK:
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case IMX8QM_SDHC2_DIV:
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resource = SC_R_SDHC_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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2019-03-05 02:32:35 +00:00
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case IMX8QM_UART0_IPG_CLK:
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case IMX8QM_UART0_CLK:
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resource = SC_R_UART_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART1_CLK:
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resource = SC_R_UART_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART2_CLK:
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resource = SC_R_UART_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART3_CLK:
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resource = SC_R_UART_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_ENET0_IPG_CLK:
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case IMX8QM_ENET0_AHB_CLK:
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case IMX8QM_ENET0_REF_DIV:
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case IMX8QM_ENET0_PTP_CLK:
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resource = SC_R_ENET_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_ENET1_IPG_CLK:
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case IMX8QM_ENET1_AHB_CLK:
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case IMX8QM_ENET1_REF_DIV:
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case IMX8QM_ENET1_PTP_CLK:
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resource = SC_R_ENET_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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default:
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if (clk->id < IMX8QM_UART0_IPG_CLK ||
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clk->id >= IMX8QM_CLK_END) {
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printf("%s(Invalid clk ID #%lu)\n",
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__func__, clk->id);
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return -EINVAL;
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}
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2021-03-24 21:26:08 +00:00
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return -EINVAL;
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2019-03-05 02:32:35 +00:00
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};
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ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
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(sc_pm_clock_rate_t *)&rate);
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if (ret) {
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printf("%s err %d\n", __func__, ret);
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return ret;
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}
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return rate;
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}
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ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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sc_pm_clk_t pm_clk;
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u32 new_rate = rate;
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u16 resource;
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int ret;
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debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
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switch (clk->id) {
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C0_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C0_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C0_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C1_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C1_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C1_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C2_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C2_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C2_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C3_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C3_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C3_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART0_CLK:
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resource = SC_R_UART_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART1_CLK:
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resource = SC_R_UART_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART2_CLK:
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resource = SC_R_UART_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART3_CLK:
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resource = SC_R_UART_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_SDHC0_IPG_CLK:
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case IMX8QM_SDHC0_CLK:
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case IMX8QM_SDHC0_DIV:
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resource = SC_R_SDHC_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_SDHC1_IPG_CLK:
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case IMX8QM_SDHC1_CLK:
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case IMX8QM_SDHC1_DIV:
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resource = SC_R_SDHC_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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2019-05-31 16:00:17 +00:00
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case IMX8QM_SDHC2_IPG_CLK:
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case IMX8QM_SDHC2_CLK:
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case IMX8QM_SDHC2_DIV:
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resource = SC_R_SDHC_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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2019-03-05 02:32:35 +00:00
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case IMX8QM_ENET0_IPG_CLK:
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case IMX8QM_ENET0_AHB_CLK:
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case IMX8QM_ENET0_REF_DIV:
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case IMX8QM_ENET0_PTP_CLK:
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case IMX8QM_ENET0_ROOT_DIV:
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resource = SC_R_ENET_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_ENET1_IPG_CLK:
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case IMX8QM_ENET1_AHB_CLK:
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case IMX8QM_ENET1_REF_DIV:
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case IMX8QM_ENET1_PTP_CLK:
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case IMX8QM_ENET1_ROOT_DIV:
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resource = SC_R_ENET_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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default:
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if (clk->id < IMX8QM_UART0_IPG_CLK ||
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clk->id >= IMX8QM_CLK_END) {
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printf("%s(Invalid clk ID #%lu)\n",
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__func__, clk->id);
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return -EINVAL;
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}
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2021-03-24 21:26:08 +00:00
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return -EINVAL;
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2019-03-05 02:32:35 +00:00
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};
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ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
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if (ret) {
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printf("%s err %d\n", __func__, ret);
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return ret;
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}
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return new_rate;
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}
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int __imx8_clk_enable(struct clk *clk, bool enable)
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{
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sc_pm_clk_t pm_clk;
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u16 resource;
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int ret;
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debug("%s(#%lu)\n", __func__, clk->id);
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switch (clk->id) {
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C0_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C0_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C0_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C1_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C1_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C1_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C2_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C2_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C2_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C3_IPG_CLK:
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2019-03-05 02:32:35 +00:00
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case IMX8QM_I2C3_CLK:
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2020-11-12 10:51:04 +00:00
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case IMX8QM_I2C3_DIV:
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2019-03-05 02:32:35 +00:00
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resource = SC_R_I2C_3;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART0_CLK:
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resource = SC_R_UART_0;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART1_CLK:
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resource = SC_R_UART_1;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART2_CLK:
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resource = SC_R_UART_2;
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pm_clk = SC_PM_CLK_PER;
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break;
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case IMX8QM_UART3_CLK:
|
|
|
|
resource = SC_R_UART_3;
|
|
|
|
pm_clk = SC_PM_CLK_PER;
|
|
|
|
break;
|
|
|
|
case IMX8QM_SDHC0_IPG_CLK:
|
|
|
|
case IMX8QM_SDHC0_CLK:
|
|
|
|
case IMX8QM_SDHC0_DIV:
|
|
|
|
resource = SC_R_SDHC_0;
|
|
|
|
pm_clk = SC_PM_CLK_PER;
|
|
|
|
break;
|
|
|
|
case IMX8QM_SDHC1_IPG_CLK:
|
|
|
|
case IMX8QM_SDHC1_CLK:
|
|
|
|
case IMX8QM_SDHC1_DIV:
|
|
|
|
resource = SC_R_SDHC_1;
|
|
|
|
pm_clk = SC_PM_CLK_PER;
|
|
|
|
break;
|
2019-05-31 16:00:17 +00:00
|
|
|
case IMX8QM_SDHC2_IPG_CLK:
|
|
|
|
case IMX8QM_SDHC2_CLK:
|
|
|
|
case IMX8QM_SDHC2_DIV:
|
|
|
|
resource = SC_R_SDHC_2;
|
|
|
|
pm_clk = SC_PM_CLK_PER;
|
|
|
|
break;
|
2019-03-05 02:32:35 +00:00
|
|
|
case IMX8QM_ENET0_IPG_CLK:
|
|
|
|
case IMX8QM_ENET0_AHB_CLK:
|
|
|
|
case IMX8QM_ENET0_REF_DIV:
|
|
|
|
case IMX8QM_ENET0_PTP_CLK:
|
|
|
|
resource = SC_R_ENET_0;
|
|
|
|
pm_clk = SC_PM_CLK_PER;
|
|
|
|
break;
|
|
|
|
case IMX8QM_ENET1_IPG_CLK:
|
|
|
|
case IMX8QM_ENET1_AHB_CLK:
|
|
|
|
case IMX8QM_ENET1_REF_DIV:
|
|
|
|
case IMX8QM_ENET1_PTP_CLK:
|
|
|
|
resource = SC_R_ENET_1;
|
|
|
|
pm_clk = SC_PM_CLK_PER;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
if (clk->id < IMX8QM_UART0_IPG_CLK ||
|
|
|
|
clk->id >= IMX8QM_CLK_END) {
|
|
|
|
printf("%s(Invalid clk ID #%lu)\n",
|
|
|
|
__func__, clk->id);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2021-03-24 21:26:08 +00:00
|
|
|
return -EINVAL;
|
2019-03-05 02:32:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
|
|
|
|
if (ret) {
|
|
|
|
printf("%s err %d\n", __func__, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|