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u-boot/arch/arm/mach-rockchip/Makefile

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rockchip: Add core SoC start-up code Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:38 +00:00
#
# Copyright (c) 2014 Google, Inc
#
# SPDX-License-Identifier: GPL-2.0+
#
rockchip: Print a message when returning to the bootrom At present if the return to bootrom fails (e.g. because you are not using the Rockchip's bootrom's pointer table in MMC) then the board prints SPL message and hangs. Print a message first if we can, to help in understanding what happened when it hangs. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Heiko Stuebner <heiko@sntech.de>
2017-04-15 19:11:31 +00:00
obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
rockchip: rk3188: Add main, spl and tpl boards The rk3188 needs 3 U-Boot stages: a tpl living in 1KB of sram, a spl the resides in the rest of the sram and loads the regular U-Boot living in regular ram. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-02-18 18:46:38 +00:00
ifdef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
else ifdef CONFIG_SPL_BUILD
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
rockchip: rk3188: Add main, spl and tpl boards The rk3188 needs 3 U-Boot stages: a tpl living in 1KB of sram, a spl the resides in the rest of the sram and loads the regular U-Boot living in regular ram. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-02-18 18:46:38 +00:00
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
cosmetic: rockchip: sort socs according to numbers Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-15 22:17:15 +00:00
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
rockchip: arm64: rk3399: add SPL support Add SPL support for rk3399, default with of-platdata enabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Drop Kconfig changes to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 08:09:05 +00:00
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
rockchip: Move bootrom helper compilation to a hidden option Right now the ROCKCHIP_SPL_BACK_TO_BROM option both triggers compilation of the bootrom hook-code as well as enabling the behaviour of loading the full U-Boot via the boot. New added socs may always need the bootrom code, while still being able to decide between loading U-Boot regularly or via the bootrom separately. So move the compilation of the bootrom code to a hidden option that gets selected by ROCKCHIP_SPL_BACK_TO_BROM, but can also be selected by other parts. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-02-18 18:46:25 +00:00
obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
rockchip: Add core SoC start-up code Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:38 +00:00
else
rockchip: rk3188: Add main, spl and tpl boards The rk3188 needs 3 U-Boot stages: a tpl living in 1KB of sram, a spl the resides in the rest of the sram and loads the regular U-Boot living in regular ram. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-02-18 18:46:38 +00:00
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
rockchip: rename board.c to rk3288-board.c Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-09-19 10:46:26 +00:00
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
rockchip: move common function from board-file to rk3036-board.c To keep it same with 3288 Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-09-19 10:46:27 +00:00
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
rockchip: Add core SoC start-up code Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-30 22:55:38 +00:00
endif
rockchip: Exclude rk_timer for ARM64 It conflicts with the generic_timer. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-14 04:22:09 +00:00
ifndef CONFIG_ARM64
rockchip: add timer driver some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-17 06:20:09 +00:00
obj-y += rk_timer.o
rockchip: Exclude rk_timer for ARM64 It conflicts with the generic_timer. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-14 04:22:09 +00:00
endif
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
rockchip: rk3188: Add core support Add the core architecture code for the rk3188. It doesn't support the SPL yet, as because of some unknown error it doesn't start yet. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Drop these defines from rk3188_common.h CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-18 18:46:36 +00:00
ifndef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
endif
cosmetic: rockchip: sort socs according to numbers Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-15 22:17:15 +00:00
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
rockchip: rk3328: add soc basic support RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-23 07:37:51 +00:00
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
rockchip: rk3368: Add core start-up code for RK3368 The RK3368 is an octa-core Cortex-A53 SoC from Rockchip. This adds basic support to chain-load U-Boot from Rockchip's miniloader. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-15 09:51:18 +00:00
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
ARM64: rockchip: add support for rk3399 SoC based evb RK3399 is a SoC from Rockchip with dual-core Cortex-A72 and quad-core Cortex-A53 CPU. It supports two USB3.0 type-C ports and two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-128MB range. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-07-19 13:16:59 +00:00
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
rockchip: Add core Soc start-up code for rv1108 RV1108 is embedded with an ARM Cortex-A7 single core and a DSP core from Rockchip. It is designed for varies application scenario such as car DVR, sports DV, secure camera and UAV camera. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-01 10:00:55 +00:00
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
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