2015-06-27 17:05:14 +00:00
|
|
|
menu "SPI Support"
|
|
|
|
|
2014-10-23 13:26:09 +00:00
|
|
|
config DM_SPI
|
|
|
|
bool "Enable Driver Model for SPI drivers"
|
|
|
|
depends on DM
|
|
|
|
help
|
2015-02-06 04:41:35 +00:00
|
|
|
Enable driver model for SPI. The SPI slave interface
|
|
|
|
(spi_setup_slave(), spi_xfer(), etc.) is then implemented by
|
|
|
|
the SPI uclass. Drivers provide methods to access the SPI
|
|
|
|
buses that they control. The uclass interface is defined in
|
|
|
|
include/spi.h. The existing spi_slave structure is attached
|
|
|
|
as 'parent data' to every slave on each bus. Slaves
|
|
|
|
typically use driver-private data instead of extending the
|
|
|
|
spi_slave structure.
|
2015-03-06 20:19:05 +00:00
|
|
|
|
2015-06-27 17:07:00 +00:00
|
|
|
if DM_SPI
|
|
|
|
|
2015-10-14 00:33:34 +00:00
|
|
|
config ALTERA_SPI
|
|
|
|
bool "Altera SPI driver"
|
|
|
|
help
|
|
|
|
Enable the Altera SPI driver. This driver can be used to
|
|
|
|
access the SPI NOR flash on platforms embedding this Altera
|
|
|
|
IP core. Please find details on the "Embedded Peripherals IP
|
|
|
|
User Guide" of Altera.
|
|
|
|
|
2016-03-16 08:59:58 +00:00
|
|
|
config ATH79_SPI
|
|
|
|
bool "Atheros SPI driver"
|
|
|
|
depends on ARCH_ATH79
|
|
|
|
help
|
|
|
|
Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used
|
|
|
|
to access SPI NOR flash and other SPI peripherals. This driver
|
|
|
|
uses driver model and requires a device tree binding to operate.
|
|
|
|
please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
|
|
|
|
|
2016-10-28 06:17:49 +00:00
|
|
|
config ATMEL_SPI
|
|
|
|
bool "Atmel SPI driver"
|
|
|
|
depends on ARCH_AT91
|
|
|
|
help
|
|
|
|
This enables driver for the Atmel SPI Controller, present on
|
2017-07-05 13:25:22 +00:00
|
|
|
many AT91 (ARM) chips. This driver can be used to access
|
|
|
|
the SPI Flash, such as AT25DF321.
|
2016-10-28 06:17:49 +00:00
|
|
|
|
2015-06-27 17:07:00 +00:00
|
|
|
config CADENCE_QSPI
|
|
|
|
bool "Cadence QSPI driver"
|
|
|
|
help
|
|
|
|
Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
|
|
|
|
used to access the SPI NOR flash on platforms embedding this
|
|
|
|
Cadence IP core.
|
|
|
|
|
|
|
|
config DESIGNWARE_SPI
|
|
|
|
bool "Designware SPI driver"
|
|
|
|
help
|
|
|
|
Enable the Designware SPI driver. This driver can be used to
|
|
|
|
access the SPI NOR flash on platforms embedding this Designware
|
|
|
|
IP core.
|
|
|
|
|
2015-06-27 10:02:19 +00:00
|
|
|
config EXYNOS_SPI
|
|
|
|
bool "Samsung Exynos SPI driver"
|
|
|
|
help
|
|
|
|
Enable the Samsung Exynos SPI driver. This driver can be used to
|
|
|
|
access the SPI NOR flash on platforms embedding this Samsung
|
|
|
|
Exynos IP core.
|
|
|
|
|
2015-06-27 08:47:06 +00:00
|
|
|
config FSL_DSPI
|
|
|
|
bool "Freescale DSPI driver"
|
|
|
|
help
|
|
|
|
Enable the Freescale DSPI driver. This driver can be used to
|
|
|
|
access the SPI NOR flash and SPI Data flash on platforms embedding
|
|
|
|
this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
|
|
|
|
use this driver.
|
|
|
|
|
2015-06-27 10:13:27 +00:00
|
|
|
config ICH_SPI
|
|
|
|
bool "Intel ICH SPI driver"
|
|
|
|
help
|
|
|
|
Enable the Intel ICH SPI driver. This driver can be used to
|
|
|
|
access the SPI NOR flash on platforms embedding this Intel
|
|
|
|
ICH IP core.
|
|
|
|
|
2016-05-19 13:56:44 +00:00
|
|
|
config MVEBU_A3700_SPI
|
|
|
|
bool "Marvell Armada 3700 SPI driver"
|
|
|
|
help
|
|
|
|
Enable the Marvell Armada 3700 SPI driver. This driver can be
|
|
|
|
used to access the SPI NOR flash on platforms embedding this
|
|
|
|
Marvell IP core.
|
|
|
|
|
2016-06-02 08:56:08 +00:00
|
|
|
config PIC32_SPI
|
|
|
|
bool "Microchip PIC32 SPI driver"
|
|
|
|
depends on MACH_PIC32
|
|
|
|
help
|
|
|
|
Enable the Microchip PIC32 SPI driver. This driver can be used
|
|
|
|
to access the SPI NOR flash, MMC-over-SPI on platforms based on
|
|
|
|
Microchip PIC32 family devices.
|
|
|
|
|
2015-09-02 01:19:37 +00:00
|
|
|
config ROCKCHIP_SPI
|
|
|
|
bool "Rockchip SPI driver"
|
|
|
|
help
|
|
|
|
Enable the Rockchip SPI driver, used to access SPI NOR flash and
|
|
|
|
other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
|
|
|
|
This uses driver model and requires a device tree binding to
|
|
|
|
operate.
|
|
|
|
|
2015-03-06 20:19:05 +00:00
|
|
|
config SANDBOX_SPI
|
|
|
|
bool "Sandbox SPI driver"
|
|
|
|
depends on SANDBOX && DM
|
|
|
|
help
|
|
|
|
Enable SPI support for sandbox. This is an emulation of a real SPI
|
|
|
|
bus. Devices can be attached to the bus using the device tree
|
|
|
|
which specifies the driver to use. As an example, see this device
|
|
|
|
tree fragment from sandbox.dts. It shows that the SPI bus has a
|
|
|
|
single flash device on chip select 0 which is emulated by the driver
|
|
|
|
for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
|
|
|
|
|
|
|
|
spi@0 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
compatible = "sandbox,spi";
|
|
|
|
cs-gpios = <0>, <&gpio_a 0>;
|
|
|
|
flash@0 {
|
|
|
|
reg = <0>;
|
|
|
|
compatible = "spansion,m25p16", "sandbox,spi-flash";
|
|
|
|
spi-max-frequency = <40000000>;
|
|
|
|
sandbox,filename = "spi.bin";
|
|
|
|
};
|
2015-06-27 17:07:00 +00:00
|
|
|
};
|
2015-06-26 23:11:11 +00:00
|
|
|
|
2017-01-22 15:04:30 +00:00
|
|
|
config STM32_QSPI
|
|
|
|
bool "STM32F7 QSPI driver"
|
|
|
|
depends on STM32F7
|
|
|
|
help
|
|
|
|
Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be
|
|
|
|
used to access the SPI NOR flash chips on platforms embedding
|
|
|
|
this ST IP core.
|
|
|
|
|
2015-06-27 10:27:53 +00:00
|
|
|
config TEGRA114_SPI
|
|
|
|
bool "nVidia Tegra114 SPI driver"
|
|
|
|
help
|
|
|
|
Enable the nVidia Tegra114 SPI driver. This driver can be used to
|
|
|
|
access the SPI NOR flash on platforms embedding this nVidia Tegra114
|
|
|
|
IP core.
|
|
|
|
|
|
|
|
This controller is different than the older SoCs SPI controller and
|
|
|
|
also register interface get changed with this controller.
|
|
|
|
|
2015-06-27 10:34:05 +00:00
|
|
|
config TEGRA20_SFLASH
|
|
|
|
bool "nVidia Tegra20 Serial Flash controller driver"
|
|
|
|
help
|
|
|
|
Enable the nVidia Tegra20 Serial Flash controller driver. This driver
|
|
|
|
can be used to access the SPI NOR flash on platforms embedding this
|
|
|
|
nVidia Tegra20 IP core.
|
|
|
|
|
2015-06-27 10:37:54 +00:00
|
|
|
config TEGRA20_SLINK
|
|
|
|
bool "nVidia Tegra20/Tegra30 SLINK driver"
|
|
|
|
help
|
|
|
|
Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
|
|
|
|
be used to access the SPI NOR flash on platforms embedding this
|
|
|
|
nVidia Tegra20/Tegra30 IP cores.
|
|
|
|
|
2015-10-12 21:50:54 +00:00
|
|
|
config TEGRA210_QSPI
|
|
|
|
bool "nVidia Tegra210 QSPI driver"
|
|
|
|
help
|
|
|
|
Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver
|
|
|
|
be used to access SPI chips on platforms embedding this
|
|
|
|
NVIDIA Tegra210 IP core.
|
|
|
|
|
2015-06-26 23:02:43 +00:00
|
|
|
config XILINX_SPI
|
|
|
|
bool "Xilinx SPI driver"
|
|
|
|
help
|
|
|
|
Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
|
|
|
|
controller support 8 bit SPI transfers only, with or w/o FIFO.
|
|
|
|
For more info on Xilinx SPI Register Definitions and Overview
|
|
|
|
see driver file - drivers/spi/xilinx_spi.c
|
|
|
|
|
2015-06-26 19:21:38 +00:00
|
|
|
config ZYNQ_SPI
|
|
|
|
bool "Zynq SPI driver"
|
2015-12-07 10:33:58 +00:00
|
|
|
depends on ARCH_ZYNQ || ARCH_ZYNQMP
|
2015-06-26 19:21:38 +00:00
|
|
|
help
|
|
|
|
Enable the Zynq SPI driver. This driver can be used to
|
|
|
|
access the SPI NOR flash on platforms embedding this Zynq
|
|
|
|
SPI IP core.
|
2015-06-27 17:05:14 +00:00
|
|
|
|
2015-08-15 18:49:38 +00:00
|
|
|
config ZYNQ_QSPI
|
|
|
|
bool "Zynq QSPI driver"
|
|
|
|
depends on ARCH_ZYNQ
|
|
|
|
help
|
|
|
|
Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
|
|
|
|
used to access the SPI NOR flash on platforms embedding this
|
|
|
|
Zynq QSPI IP core. This IP is used to connect the flash in
|
|
|
|
4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
|
|
|
|
|
2015-06-27 17:07:00 +00:00
|
|
|
endif # if DM_SPI
|
|
|
|
|
2017-04-13 06:09:55 +00:00
|
|
|
config SOFT_SPI
|
|
|
|
bool "Soft SPI driver"
|
|
|
|
help
|
|
|
|
Enable Soft SPI driver. This driver is to use GPIO simulate
|
|
|
|
the SPI protocol.
|
|
|
|
|
2015-06-27 09:51:36 +00:00
|
|
|
config FSL_ESPI
|
|
|
|
bool "Freescale eSPI driver"
|
|
|
|
help
|
|
|
|
Enable the Freescale eSPI driver. This driver can be used to
|
|
|
|
access the SPI interface and SPI NOR flash on platforms embedding
|
|
|
|
this Freescale eSPI IP core.
|
|
|
|
|
2016-09-03 07:28:33 +00:00
|
|
|
config FSL_QSPI
|
|
|
|
bool "Freescale QSPI driver"
|
|
|
|
help
|
|
|
|
Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
|
|
|
|
used to access the SPI NOR flash on platforms embedding this
|
|
|
|
Freescale IP core.
|
|
|
|
|
2017-11-23 06:19:36 +00:00
|
|
|
config ATCSPI200_SPI
|
|
|
|
bool "Andestech ATCSPI200 SPI driver"
|
nds32: spi: Support spi dm driver.
Support spi driver and can detect MX25U1635E flash on AE3XX board.
Verification:
sf probe 0:0 50000000 0
spi_flash_std_probe(sf_Probr.c)
spi_flash_probe_slave(sf_Probr.c)
SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
NDS32 # sf test 0x100000 0x1000
SPI flash test:
0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
1 check: 15 ticks, 266 KiB/s 2.128 Mbps
2 write: 21 ticks, 190 KiB/s 1.520 Mbps
3 read: 11 ticks, 363 KiB/s 2.904 Mbps
Test passed
0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
1 check: 15 ticks, 266 KiB/s 2.128 Mbps
2 write: 21 ticks, 190 KiB/s 1.520 Mbps
3 read: 11 ticks, 363 KiB/s 2.904 Mbps
Signed-off-by: rick <rick@andestech.com>
2017-08-28 07:08:01 +00:00
|
|
|
help
|
2017-11-23 06:19:36 +00:00
|
|
|
Enable the Andestech ATCSPI200 SPI driver. This driver can be
|
|
|
|
used to access the SPI flash on AE3XX and AE250 platforms embedding
|
|
|
|
this Andestech IP core.
|
nds32: spi: Support spi dm driver.
Support spi driver and can detect MX25U1635E flash on AE3XX board.
Verification:
sf probe 0:0 50000000 0
spi_flash_std_probe(sf_Probr.c)
spi_flash_probe_slave(sf_Probr.c)
SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
NDS32 # sf test 0x100000 0x1000
SPI flash test:
0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
1 check: 15 ticks, 266 KiB/s 2.128 Mbps
2 write: 21 ticks, 190 KiB/s 1.520 Mbps
3 read: 11 ticks, 363 KiB/s 2.904 Mbps
Test passed
0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
1 check: 15 ticks, 266 KiB/s 2.128 Mbps
2 write: 21 ticks, 190 KiB/s 1.520 Mbps
3 read: 11 ticks, 363 KiB/s 2.904 Mbps
Signed-off-by: rick <rick@andestech.com>
2017-08-28 07:08:01 +00:00
|
|
|
|
2015-06-27 17:07:00 +00:00
|
|
|
config TI_QSPI
|
|
|
|
bool "TI QSPI driver"
|
|
|
|
help
|
|
|
|
Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
|
|
|
|
This driver support spi flash single, quad and memory reads.
|
|
|
|
|
2017-07-06 08:33:25 +00:00
|
|
|
config MPC8XX_SPI
|
|
|
|
bool "MPC8XX SPI Driver"
|
|
|
|
depends on 8xx
|
|
|
|
help
|
|
|
|
Enable support for SPI on MPC8XX
|
|
|
|
|
2017-07-27 03:25:29 +00:00
|
|
|
config OMAP3_SPI
|
|
|
|
bool "McSPI driver for OMAP"
|
|
|
|
help
|
|
|
|
SPI master controller for OMAP24XX and later Multichannel SPI
|
|
|
|
(McSPI). This driver be used to access SPI chips on platforms
|
|
|
|
embedding this OMAP3 McSPI IP core.
|
|
|
|
|
2015-06-27 17:05:14 +00:00
|
|
|
endmenu # menu "SPI Support"
|