u-boot/include/dt-bindings/memory/tegra30-mc.h

#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
#define DT_BINDINGS_MEMORY_TEGRA30_MC_H

#define TEGRA_SWGROUP_PTC	0
#define TEGRA_SWGROUP_DC	1
#define TEGRA_SWGROUP_DCB	2
#define TEGRA_SWGROUP_EPP	3
#define TEGRA_SWGROUP_G2	4
#define TEGRA_SWGROUP_MPE	5
#define TEGRA_SWGROUP_VI	6
#define TEGRA_SWGROUP_AFI	7
#define TEGRA_SWGROUP_AVPC	8
#define TEGRA_SWGROUP_NV	9
#define TEGRA_SWGROUP_NV2	10
#define TEGRA_SWGROUP_HDA	11
#define TEGRA_SWGROUP_HC	12
#define TEGRA_SWGROUP_PPCS	13
#define TEGRA_SWGROUP_SATA	14
#define TEGRA_SWGROUP_VDE	15
#define TEGRA_SWGROUP_MPCORELP	16
#define TEGRA_SWGROUP_MPCORE	17
#define TEGRA_SWGROUP_ISP	18

#endif
ARM: tegra: pull Tegra30 SoC DT from Linux v4.7 The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Modification of PCIe memory region addresses. The HW memory layout is programmable, so this should work fine, and Beaver PCIe was tested without issue. * Removal of pcie_xclk from the PCIe node and clock binding header. This clock doesn't exist and isn't used; only a reset with this ID exists. * Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Changed the phy_type value for the second USB port. This required board DTs to be updated to keep the same configuration. * Boards need to define the clk32k_in clock that feeds the Tegra PMC. * Addition of tegra30-mc.h since tegra30.dtsi now includes it. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot. * Node sort order fixes. Remaining deltas relative to the Linux DT: * None. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> 2016-09-13 16:45:51 +00:00			`#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H`
			`#define DT_BINDINGS_MEMORY_TEGRA30_MC_H`

			`#define TEGRA_SWGROUP_PTC 0`
			`#define TEGRA_SWGROUP_DC 1`
			`#define TEGRA_SWGROUP_DCB 2`
			`#define TEGRA_SWGROUP_EPP 3`
			`#define TEGRA_SWGROUP_G2 4`
			`#define TEGRA_SWGROUP_MPE 5`
			`#define TEGRA_SWGROUP_VI 6`
			`#define TEGRA_SWGROUP_AFI 7`
			`#define TEGRA_SWGROUP_AVPC 8`
			`#define TEGRA_SWGROUP_NV 9`
			`#define TEGRA_SWGROUP_NV2 10`
			`#define TEGRA_SWGROUP_HDA 11`
			`#define TEGRA_SWGROUP_HC 12`
			`#define TEGRA_SWGROUP_PPCS 13`
			`#define TEGRA_SWGROUP_SATA 14`
			`#define TEGRA_SWGROUP_VDE 15`
			`#define TEGRA_SWGROUP_MPCORELP 16`
			`#define TEGRA_SWGROUP_MPCORE 17`
			`#define TEGRA_SWGROUP_ISP 18`

			`#endif`