2018-08-27 10:27:09 +00:00
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
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# Lokesh Vutla <lokeshvutla@ti.com>
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obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
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arm: K3: j721e: Add basic support for J721E SoC definition
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Add base support for J721E SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2019-06-13 04:59:42 +00:00
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obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
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arm: mach-k3: Add basic support for AM642 SoC definition
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.
Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
peripherals.
* Centralized System Controller for Security, Power, and Resource
Management (DMSC).
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-04-23 16:27:32 +00:00
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obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
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2018-08-27 10:27:13 +00:00
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obj-$(CONFIG_ARM64) += arm64-mmu.o
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2018-11-15 05:34:50 +00:00
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obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
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2019-04-12 16:54:45 +00:00
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obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
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2020-07-15 21:02:36 +00:00
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obj-$(CONFIG_ARM64) += cache.o
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2019-06-04 22:55:47 +00:00
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ifeq ($(CONFIG_SPL_BUILD),y)
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obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
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endif
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2018-11-02 14:21:05 +00:00
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obj-y += common.o
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