mirror of
https://github.com/AsahiLinux/u-boot
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79 lines
3.3 KiB
ReStructuredText
79 lines
3.3 KiB
ReStructuredText
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Calxeda Highbank/Midway board support
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=====================================
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The Calxeda ECX-1000 ("Highbank") and ECX-2000 ("Midway") were ARM based
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servers, providing high-density cluster systems. A single motherboard could
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host between 12 and 48 nodes, each with their own quad-core ARMv7
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processor, private DRAM and peripherals, connected through a high-bandwith
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and low-latency "fabric" network. Multiple motherboards could be connected
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together, to extend this fabric.
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For the purpose of U-Boot we just care about a single node, this can be
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used as a single system, just using the fabric to connect to some Ethernet
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network. Each node boots on its own, either from a local hard disk, or
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via the network.
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The earlier ECX-1000 nodes ("Highbank") contain four ARM Cortex-A9 cores,
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a Cortex-M3 system controller, three 10GBit/s MACs and five SATA
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controllers. The DRAM is limited to 4GB.
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The later ECX-2000 nodes ("Midway") use four Cortex-A15 cores, alongside
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two Cortex-A7 management cores, and support up to 32GB of DRAM, while
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keeping the other peripherals.
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For the purpose of U-Boot those two SoCs are very similar, so we offer
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one build target. The subtle differences are handled at runtime.
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Calxeda as a company is long defunct, and the remaining systems are
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considered legacy at this point.
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Bgilding U-Boot
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---------------
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There is only one defconfig to cover both systems::
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$ make highbank_defconfig
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$ make
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This will create ``u-boot.bin``, which could become part of the firmware update
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package, or could be chainloaded by the existing U-Boot, see below for more
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details.
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Boot process
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------------
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Upon powering up a node (which would be controlled by some BMC style
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management controller on the motherboard), the system controller ("ECME")
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would start and do some system initialisation (fabric registration,
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DRAM init, clock setup). It would load the device tree binary, some secure
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monitor code (``a9boot``/``a15boot``) and a U-Boot binary from SPI flash
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into DRAM, then power up the actual application cores (ARM Cortex-A9/A15).
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They would start executing ``a9boot``/``a15boot``, registering the PSCI SMC
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handlers, then dropping into U-Boot, but in non-secure state (HYP mode on
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the A15s).
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U-Boot would act as a mere loader, trying to find some ``boot.scr`` file on
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the local hard disks, or reverting to PXE boot.
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Updating U-Boot
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---------------
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The U-Boot binary is loaded from SPI flash, which is controlled exclusively
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by the ECME. This can be reached via IPMI using the LANplus transport protocol.
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Updating the SPI flash content requires vendor specific additions to the
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IPMI protocol, support for which was never upstreamed to ipmitool or
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FreeIPMI. Some older repositories for `ipmitool`_, the `pyipmi`_ library and
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a Python `management script`_ to update the SPI flash can be found on Github.
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A simpler and safer way to get an up-to-date U-Boot running, is chainloading
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it via the legacy U-Boot::
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$ mkimage -A arm -O u-boot -T standalone -C none -a 0x8000 -e 0x8000 \
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-n U-Boot -d u-boot.bin u-boot-highbank.img
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Then load this image file, either from hard disk, or via TFTP, from the
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existing U-Boot, and execute it with bootm::
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=> tftpboot 0x8000 u-boot-highbank.img
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=> bootm
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.. _`ipmitool`: https://github.com/Cynerva/ipmitool
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.. _`pyipmi`: https://pypi.org/project/pyipmi/
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.. _`management script`: https://github.com/Cynerva/cxmanage
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