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u-boot/arch/riscv/lib/interrupts.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
/*
* Copyright (c) 2016-17 Microsemi Corporation.
* Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
*
* Copyright (C) 2017 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
*
* Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
*/
arch/riscv: add semihosting support for RISC-V We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-12-07 11:42:35 +00:00
#include <linux/compat.h>
riscv: additional crash information If an exception occurs, the relocated program counter and return address are required for an analysis. With this patch you get: => exception undefined Unhandled exception: Illegal instruction EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted We can use the relocated addresses to find the involved functions in u.boot.map: .text.do_undefined 0x0000000080007908 0x8 cmd/built-in.o .text.cmd_process 0x000000008000dfcc 0x11a common/built-in.o 0x000000008000dfcc cmd_process If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: => setenv efi_selftest exception => bootefi selftest Unhandled exception: Illegal instruction EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); asm volatile (".word 0xffffffff\n"); 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-01 15:15:39 +00:00
#include <efi_loader.h>
common: Move hang() to the same header as panic() At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-28 17:45:07 +00:00
#include <hang.h>
common: Move interrupt functions into a new header These functions do not use driver model but are fairly widely used in U-Boot. But it is not clear that they will use driver model anytime soon, so we don't want to label them as 'legacy'. Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it is widely used in U-Boot already. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-14 19:57:41 +00:00
#include <irq_func.h>
common: Drop asm/global_data.h from common header Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-10-31 03:38:53 +00:00
#include <asm/global_data.h>
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/encoding.h>
arch/riscv: add semihosting support for RISC-V We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-12-07 11:42:35 +00:00
#include <semihosting.h>
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
riscv: additional crash information If an exception occurs, the relocated program counter and return address are required for an analysis. With this patch you get: => exception undefined Unhandled exception: Illegal instruction EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted We can use the relocated addresses to find the involved functions in u.boot.map: .text.do_undefined 0x0000000080007908 0x8 cmd/built-in.o .text.cmd_process 0x000000008000dfcc 0x11a common/built-in.o 0x000000008000dfcc cmd_process If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: => setenv efi_selftest exception => bootefi selftest Unhandled exception: Illegal instruction EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); asm volatile (".word 0xffffffff\n"); 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-01 15:15:39 +00:00
DECLARE_GLOBAL_DATA_PTR;
static void show_efi_loaded_images(uintptr_t epc)
{
efi_print_image_infos((void *)epc);
}
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
static void show_regs(struct pt_regs *regs)
{
#ifdef CONFIG_SHOW_REGS
riscv: reset after crash If an exception occurs on ARM or x86, we call panic() which will try to reset the board. Do the same on RISC-V. To avoid -Werror=format-zero-length move a '\n' to the string passed to panic. We don't need a message here as depending on CONFIG_PANIC_HANG we will either see ### ERROR ### Please RESET the board ### or resetting ... as next message. Reviewed-by: Rick Chen <rick@andestech.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-12-02 13:36:26 +00:00
printf("\nSP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n",
riscv: additional crash information If an exception occurs, the relocated program counter and return address are required for an analysis. With this patch you get: => exception undefined Unhandled exception: Illegal instruction EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted We can use the relocated addresses to find the involved functions in u.boot.map: .text.do_undefined 0x0000000080007908 0x8 cmd/built-in.o .text.cmd_process 0x000000008000dfcc 0x11a common/built-in.o 0x000000008000dfcc cmd_process If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: => setenv efi_selftest exception => bootefi selftest Unhandled exception: Illegal instruction EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); asm volatile (".word 0xffffffff\n"); 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-01 15:15:39 +00:00
regs->sp, regs->gp, regs->tp);
printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n",
regs->t0, regs->t1, regs->t2);
printf("S0: " REG_FMT " S1: " REG_FMT " A0: " REG_FMT "\n",
regs->s0, regs->s1, regs->a0);
printf("A1: " REG_FMT " A2: " REG_FMT " A3: " REG_FMT "\n",
regs->a1, regs->a2, regs->a3);
printf("A4: " REG_FMT " A5: " REG_FMT " A6: " REG_FMT "\n",
regs->a4, regs->a5, regs->a6);
printf("A7: " REG_FMT " S2: " REG_FMT " S3: " REG_FMT "\n",
regs->a7, regs->s2, regs->s3);
printf("S4: " REG_FMT " S5: " REG_FMT " S6: " REG_FMT "\n",
regs->s4, regs->s5, regs->s6);
printf("S7: " REG_FMT " S8: " REG_FMT " S9: " REG_FMT "\n",
regs->s7, regs->s8, regs->s9);
printf("S10: " REG_FMT " S11: " REG_FMT " T3: " REG_FMT "\n",
regs->s10, regs->s11, regs->t3);
riscv: reset after crash If an exception occurs on ARM or x86, we call panic() which will try to reset the board. Do the same on RISC-V. To avoid -Werror=format-zero-length move a '\n' to the string passed to panic. We don't need a message here as depending on CONFIG_PANIC_HANG we will either see ### ERROR ### Please RESET the board ### or resetting ... as next message. Reviewed-by: Rick Chen <rick@andestech.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-12-02 13:36:26 +00:00
printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n",
riscv: additional crash information If an exception occurs, the relocated program counter and return address are required for an analysis. With this patch you get: => exception undefined Unhandled exception: Illegal instruction EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted We can use the relocated addresses to find the involved functions in u.boot.map: .text.do_undefined 0x0000000080007908 0x8 cmd/built-in.o .text.cmd_process 0x000000008000dfcc 0x11a common/built-in.o 0x000000008000dfcc cmd_process If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: => setenv efi_selftest exception => bootefi selftest Unhandled exception: Illegal instruction EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); asm volatile (".word 0xffffffff\n"); 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-01 15:15:39 +00:00
regs->t4, regs->t5, regs->t6);
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
#endif
}
riscv: show code leading to exception To make analyzing exceptions easier output the code that leads to it. We already do the same on the ARM platform. Here is an example: => exception ebreak Unhandled exception: Breakpoint EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000 EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) To disassemble the code we can use the decodecode script: $ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \ CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) All code ======== 0: 2785 addiw a5,a5,1 2: 07a00693 li a3,122 6: fef6dce3 bge a3,a5,0xfffffffffffffffe a: 47a5 li a5,9 c: 00e7d563 bge a5,a4,0x16 10:* 9002 ebreak <-- trapping instruction ... Code starting with the faulting instruction =========================================== 0: 9002 ebreak ... As it is not always clear if the first 16 bits are at the start or in the middle of a 32bit instruction it may become necessary to strip the first u16 from the output before calling decodecode to get the correct disassembled code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-09-04 08:36:49 +00:00
/**
* instr_len() - get instruction length
*
* @i: low 16 bits of the instruction
* Return: number of u16 in instruction
*/
static int instr_len(u16 i)
{
if ((i & 0x03) != 0x03)
return 1;
/* Instructions with more than 32 bits are not yet specified */
return 2;
}
/**
* show_code() - display code leading to exception
*
* @epc: program counter
*/
static void show_code(ulong epc)
{
u16 *pos = (u16 *)(epc & ~1UL);
int i, len = instr_len(*pos);
printf("\nCode: ");
for (i = -8; i; ++i)
printf("%04x ", pos[i]);
printf("(");
for (i = 0; i < len; ++i)
printf("%04x%s", pos[i], i + 1 == len ? ")\n" : " ");
}
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
riscv: Adjust the _exit_trap() position to come before handle_trap() With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:44 +00:00
{
static const char * const exception_code[] = {
"Instruction address misaligned",
"Instruction access fault",
"Illegal instruction",
"Breakpoint",
"Load address misaligned",
"Load access fault",
"Store/AMO address misaligned",
"Store/AMO access fault",
"Environment call from U-mode",
"Environment call from S-mode",
"Reserved",
"Environment call from M-mode",
"Instruction page fault",
"Load page fault",
"Reserved",
"Store/AMO page fault",
};
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
if (code < ARRAY_SIZE(exception_code))
printf("Unhandled exception: %s\n", exception_code[code]);
else
printf("Unhandled exception code: %ld\n", code);
riscv: Adjust the _exit_trap() position to come before handle_trap() With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:44 +00:00
riscv: additional crash information If an exception occurs, the relocated program counter and return address are required for an analysis. With this patch you get: => exception undefined Unhandled exception: Illegal instruction EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted We can use the relocated addresses to find the involved functions in u.boot.map: .text.do_undefined 0x0000000080007908 0x8 cmd/built-in.o .text.cmd_process 0x000000008000dfcc 0x11a common/built-in.o 0x000000008000dfcc cmd_process If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: => setenv efi_selftest exception => bootefi selftest Unhandled exception: Illegal instruction EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); asm volatile (".word 0xffffffff\n"); 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-01 15:15:39 +00:00
printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n",
epc, regs->ra, tval);
riscv: Ensure gp is NULL or points to valid data This ensures constructs like `if (gd & gd->...) { ... }` work when accessing the global data pointer. Without this change, it was possible for a very early trap to cause _exit_trap to directly or indirectly (through printf) to read arbitrary memory. This could cause a second trap, preventing show_regs from being printed. printf (and specifically puts) uses gd to determine what function to print with. These functions in turn use gd to find the serial device, etc. However, before accessing gd, puts first checks to see if it is non-NULL. This indicates an existing (perhaps undocumented) assumption that either gd is NULL or it is completely valid. Before this patch, gd either points to unexpected data (because it retains the value it did from the prior-stage) or points to uninitialized data (because it has not yet been initialized by board_init_f_init_reserve) until the hart has acquired available_harts_lock. This can cause two problems, depending on the value of gd->flags. If GD_FLG_SERIAL_READY is unset, then some garbage data will be printed to stdout, but there will not be a second trap. However, if GD_FLG_SERIAL_READY is set, then puts will try to print with serial_puts, which will likely cause a second trap. After this patch, gd is zero up until either a hart has set it in wait_for_gd_init, or until it is set by arch_init_gd. This prevents its usage before its data is initialized because both handle_trap and puts ensure that gd is nonzero before using it. After gd has been set, it is OK to access it because its data has been cleared (and so flags is valid). XIP cannot use locks because flash is not writable. This leaves it vulnerable to the same class of bugs regarding already-pending IPIs as before this series. Fixing that would require finding another method of synchronization, which is outside the scope of this series. Fixes: 7c6ca03eae ("riscv: additional crash information") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-21 11:51:40 +00:00
/* Print relocation adjustments, but only if gd is initialized */
if (gd && gd->flags & GD_FLG_RELOC)
riscv: reset after crash If an exception occurs on ARM or x86, we call panic() which will try to reset the board. Do the same on RISC-V. To avoid -Werror=format-zero-length move a '\n' to the string passed to panic. We don't need a message here as depending on CONFIG_PANIC_HANG we will either see ### ERROR ### Please RESET the board ### or resetting ... as next message. Reviewed-by: Rick Chen <rick@andestech.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-12-02 13:36:26 +00:00
printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n",
riscv: additional crash information If an exception occurs, the relocated program counter and return address are required for an analysis. With this patch you get: => exception undefined Unhandled exception: Illegal instruction EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted We can use the relocated addresses to find the involved functions in u.boot.map: .text.do_undefined 0x0000000080007908 0x8 cmd/built-in.o .text.cmd_process 0x000000008000dfcc 0x11a common/built-in.o 0x000000008000dfcc cmd_process If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: => setenv efi_selftest exception => bootefi selftest Unhandled exception: Illegal instruction EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); asm volatile (".word 0xffffffff\n"); 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-01 15:15:39 +00:00
epc - gd->reloc_off, regs->ra - gd->reloc_off);
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
show_regs(regs);
riscv: show code leading to exception To make analyzing exceptions easier output the code that leads to it. We already do the same on the ARM platform. Here is an example: => exception ebreak Unhandled exception: Breakpoint EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000 EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) To disassemble the code we can use the decodecode script: $ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \ CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) All code ======== 0: 2785 addiw a5,a5,1 2: 07a00693 li a3,122 6: fef6dce3 bge a3,a5,0xfffffffffffffffe a: 47a5 li a5,9 c: 00e7d563 bge a5,a4,0x16 10:* 9002 ebreak <-- trapping instruction ... Code starting with the faulting instruction =========================================== 0: 9002 ebreak ... As it is not always clear if the first 16 bits are at the start or in the middle of a 32bit instruction it may become necessary to strip the first u16 from the output before calling decodecode to get the correct disassembled code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-09-04 08:36:49 +00:00
show_code(epc);
riscv: additional crash information If an exception occurs, the relocated program counter and return address are required for an analysis. With this patch you get: => exception undefined Unhandled exception: Illegal instruction EPC: 0000000080595908 RA: 000000008059c0c6 TVAL: 000000008030c01e EPC: 0000000080007908 RA: 000000008000e0c6 reloc adjusted We can use the relocated addresses to find the involved functions in u.boot.map: .text.do_undefined 0x0000000080007908 0x8 cmd/built-in.o .text.cmd_process 0x000000008000dfcc 0x11a common/built-in.o 0x000000008000dfcc cmd_process If an exception occurs in an UEFI binary additionally the load addresses of the UEFI binaries are needed. With this patch: => setenv efi_selftest exception => bootefi selftest Unhandled exception: Illegal instruction EPC: 000000008042e18a RA: 000000008042e18a TVAL: 000000008030c01e EPC: 000000007fea018a RA: 000000007fea018a reloc adjusted UEFI image [0x0000000000000000:0xffffffffffffffff] '/\selftest' UEFI image [0x000000008042e000:0x000000008042e43f] pc=0x18a '/bug.efi' The value pc=0x18a matches the position of the illegal instruction in efi_selftest_miniapp_exception.efi (loaded as /bug.efi); asm volatile (".word 0xffffffff\n"); 00000180 93 85 C5 11 1C 64 22 85 82 97 FF FF FF FF 1C 64 Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-08-01 15:15:39 +00:00
show_efi_loaded_images(epc);
riscv: reset after crash If an exception occurs on ARM or x86, we call panic() which will try to reset the board. Do the same on RISC-V. To avoid -Werror=format-zero-length move a '\n' to the string passed to panic. We don't need a message here as depending on CONFIG_PANIC_HANG we will either see ### ERROR ### Please RESET the board ### or resetting ... as next message. Reviewed-by: Rick Chen <rick@andestech.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-12-02 13:36:26 +00:00
panic("\n");
riscv: Adjust the _exit_trap() position to come before handle_trap() With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:44 +00:00
}
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
int interrupt_init(void)
{
return 0;
}
/*
* enable interrupts
*/
void enable_interrupts(void)
{
}
/*
* disable interrupts
*/
int disable_interrupts(void)
{
return 0;
}
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
ulong handle_trap(ulong cause, ulong epc, ulong tval, struct pt_regs *regs)
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
{
riscv: Add kconfig option to run U-Boot in S-mode This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-03 05:27:40 +00:00
ulong is_irq, irq;
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
riscv: restore global data pointer in trap handler The gp register is used to store U-Boot's global data pointer. We should not assume that an UEFI application leaves the gp register unchanged as the UEFI specifications does not define who is the owner of the gp and tp registers. So the following sequence should be followed in the trap handler: * save the caller's gp register * restore the global data pointer * serve interrupts or print crash dump and reset * restore the caller's gp register Cc: Abner Chang <abner.chang@hpe.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-26 05:50:36 +00:00
/* An UEFI application may have changed gd. Restore U-Boot's gd. */
efi_restore_gd();
arch/riscv: add semihosting support for RISC-V We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-12-07 11:42:35 +00:00
if (cause == CAUSE_BREAKPOINT &&
CONFIG_IS_ENABLED(SEMIHOSTING_FALLBACK)) {
ulong pre_addr = epc - 4, post_addr = epc + 4;
/* Check for prior and post addresses to be in same page. */
if ((pre_addr & ~(PAGE_SIZE - 1)) ==
(post_addr & ~(PAGE_SIZE - 1))) {
u32 pre = *(u32 *)pre_addr;
u32 post = *(u32 *)post_addr;
/* Check for semihosting, i.e.:
* slli zero,zero,0x1f
* ebreak
* srai zero,zero,0x7
*/
if (pre == 0x01f01013 && post == 0x40705013) {
disable_semihosting();
epc += 4;
return epc;
}
}
}
riscv: Add kconfig option to run U-Boot in S-mode This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-03 05:27:40 +00:00
is_irq = (cause & MCAUSE_INT);
irq = (cause & ~MCAUSE_INT);
if (is_irq) {
switch (irq) {
case IRQ_M_EXT:
case IRQ_S_EXT:
external_interrupt(0); /* handle external interrupt */
break;
case IRQ_M_TIMER:
case IRQ_S_TIMER:
timer_interrupt(0); /* handle timer interrupt */
break;
default:
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
_exit_trap(cause, epc, tval, regs);
riscv: Add kconfig option to run U-Boot in S-mode This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-03 05:27:40 +00:00
break;
};
} else {
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
_exit_trap(cause, epc, tval, regs);
riscv: Add kconfig option to run U-Boot in S-mode This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-03 05:27:40 +00:00
}
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
return epc;
}
/*
*Entry Point for PLIC Interrupt Handler
*/
__attribute__((weak)) void external_interrupt(struct pt_regs *regs)
{
}
__attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
{
}
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