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25 lines
1.1 KiB
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25 lines
1.1 KiB
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.. SPDX-License-Identifier: GPL-2.0+
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.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
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Cougar Canyon 2 CRB
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===================
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This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
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with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
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website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
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time of writing) in the board directory and rename it to fsp.bin.
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Now build U-Boot and obtain u-boot.rom::
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$ make cougarcanyon2_defconfig
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$ make all
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The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
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the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
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and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
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flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
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this image to the SPI-0 flash according to the board manual just once and we are
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all set. For programming U-Boot we just need to program SPI-1 flash. Since the
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default u-boot.rom image for this board is set to 2MB, it should be programmed
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to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
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