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u-boot/arch/riscv/dts/microchip-mpfs.dtsi

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riscv: dts: Split Microchip device tree The device tree split into .dtsi and .dts files, common device node for eMMC/SD, enable I2C1, UART1 for console instead of UART0, enable the DDR 2GB memory and in that 288MB memory is reserved for fabric buffer. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-11-17 12:51:17 +00:00
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */
#include "dt-bindings/clock/microchip-mpfs-clock.h"
#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h"
#include "dt-bindings/interrupt-controller/riscv-hart.h"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Microchip PolarFire SoC";
compatible = "microchip,mpfs";
chosen {
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
clocks = <&clkcfg CLK_CPU>;
status = "disabled";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
operating-points = <
/* kHz uV */
600000 1100000
300000 950000
150000 750000
>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
riscv: dts: fix the mpfs's reference clock frequency The initial devicetree for PolarFire SoC incorrectly created a fixed frequency clock in the devicetree to represent the msspll, but the msspll is not a fixed frequency clock. The actual reference clock on a board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit. Swap the incorrect representation of the msspll out for the actual reference clock. Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-10-25 07:58:49 +00:00
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
riscv: dts: Split Microchip device tree The device tree split into .dtsi and .dts files, common device node for eMMC/SD, enable I2C1, UART1 for console instead of UART0, enable the DDR 2GB memory and in that 288MB memory is reserved for fabric buffer. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-11-17 12:51:17 +00:00
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "microchip,mpfs-soc", "simple-bus";
ranges;
clint: clint@2000000 {
compatible = "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended =
<&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER
&cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER
&cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER
&cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER
&cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>;
};
cachecontroller: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
reg = <0x0 0x2010000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_L2_METADATA_CORR
PLIC_INT_L2_METADATA_UNCORR
PLIC_INT_L2_DATA_CORR>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
};
pdma: pdma@3000000 {
compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR
PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR
PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR
PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>;
#dma-cells = <1>;
};
plic: interrupt-controller@c000000 {
compatible = "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
#interrupt-cells = <1>;
riscv,ndev = <186>;
interrupt-controller;
interrupts-extended = <&cpu0_intc HART_INT_M_EXT
&cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT
&cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT
&cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT
&cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
};
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
riscv: dts: fix the mpfs's reference clock frequency The initial devicetree for PolarFire SoC incorrectly created a fixed frequency clock in the devicetree to represent the msspll, but the msspll is not a fixed frequency clock. The actual reference clock on a board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit. Swap the incorrect representation of the msspll out for the actual reference clock. Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
2022-10-25 07:58:49 +00:00
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
riscv: dts: Split Microchip device tree The device tree split into .dtsi and .dts files, common device node for eMMC/SD, enable I2C1, UART1 for console instead of UART0, enable the DDR 2GB memory and in that 288MB memory is reserved for fabric buffer. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-11-17 12:51:17 +00:00
reg-names = "mss_sysreg";
clocks = <&refclk>;
#clock-cells = <1>;
clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
"mac0", "mac1", "mmc", "timer", /* 4-7 */
"mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
"mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
"i2c1", "can0", "can1", "usb", /* 16-19 */
"rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
"gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
"fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
};
/* Common node entry for eMMC/SD */
mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc","cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
clocks = <&clkcfg CLK_MMC>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMC_MAIN PLIC_INT_MMC_WAKEUP>;
max-frequency = <200000000>;
status = "disabled";
};
uart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMUART0>;
clocks = <&clkcfg CLK_MMUART0>;
status = "disabled"; /* Reserved for the HSS */
};
uart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMUART1>;
clocks = <&clkcfg CLK_MMUART1>;
status = "disabled";
};
uart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMUART2>;
clocks = <&clkcfg CLK_MMUART2>;
status = "disabled";
};
uart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMUART3>;
clocks = <&clkcfg CLK_MMUART3>;
status = "disabled";
};
uart4: serial@20106000 {
compatible = "ns16550a";
reg = <0x0 0x20106000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MMUART4>;
clocks = <&clkcfg CLK_MMUART4>;
status = "disabled";
};
spi0: spi@20108000 {
compatible = "microchip,mpfs-spi";
reg = <0x0 0x20108000 0x0 0x1000>;
clocks = <&clkcfg CLK_SPI0>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_SPI0>;
num-cs = <8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@20109000 {
compatible = "microchip,mpfs-spi";
reg = <0x0 0x20109000 0x0 0x1000>;
clocks = <&clkcfg CLK_SPI1>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_SPI1>;
num-cs = <8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@2010a000 {
compatible = "microchip,mpfs-i2c";
reg = <0x0 0x2010a000 0x0 0x1000>;
clocks = <&clkcfg CLK_I2C0>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_I2C0_MAIN>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@2010b000 {
compatible = "microchip,mpfs-i2c";
reg = <0x0 0x2010b000 0x0 0x1000>;
clocks = <&clkcfg CLK_I2C1>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_I2C1_MAIN>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
can0: can@2010c000 {
compatible = "microchip,mpfs-can-uio";
reg = <0x0 0x2010c000 0x0 0x1000>;
clocks = <&clkcfg CLK_CAN0>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_CAN0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
can1: can@2010d000 {
compatible = "microchip,mpfs-can-uio";
reg = <0x0 0x2010d000 0x0 0x1000>;
clocks = <&clkcfg CLK_CAN1>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_CAN1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MAC0_INT
PLIC_INT_MAC0_QUEUE1
PLIC_INT_MAC0_QUEUE2
PLIC_INT_MAC0_QUEUE3
PLIC_INT_MAC0_EMAC
PLIC_INT_MAC0_MMSL>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mac1: ethernet@20112000 {
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_MAC1_INT
PLIC_INT_MAC1_QUEUE1
PLIC_INT_MAC1_QUEUE2
PLIC_INT_MAC1_QUEUE3
PLIC_INT_MAC1_EMAC
PLIC_INT_MAC1_MMSL>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
gpio0: gpio@20120000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20120000 0x0 0x1000>;
reg-names = "control";
clocks = <&clkcfg CLK_GPIO0>;
interrupt-parent = <&plic>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio@20121000 {
compatible = "microchip,mpfs-gpio";
reg = <000 0x20121000 0x0 0x1000>;
reg-names = "control";
clocks = <&clkcfg CLK_GPIO1>;
interrupt-parent = <&plic>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio@20122000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20122000 0x0 0x1000>;
reg-names = "control";
clocks = <&clkcfg CLK_GPIO2>;
interrupt-parent = <&plic>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
rtc: rtc@20124000 {
compatible = "microchip,mpfs-rtc";
reg = <0x0 0x20124000 0x0 0x1000>;
clocks = <&clkcfg CLK_RTC>;
clock-names = "rtc";
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
usb: usb@20201000 {
compatible = "microchip,mpfs-usb-host";
reg = <0x0 0x20201000 0x0 0x1000>;
reg-names = "mc","control";
clocks = <&clkcfg CLK_USB>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;
interrupt-names = "dma","mc";
dr_mode = "host";
status = "disabled";
};
qspi: qspi@21000000 {
compatible = "microchip,mpfs-qspi";
reg = <0x0 0x21000000 0x0 0x1000>;
clocks = <&clkcfg CLK_QSPI>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_QSPI>;
num-cs = <8>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mbox: mailbox@37020000 {
compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_G5C_MESSAGE>;
#mbox-cells = <1>;
status = "disabled";
};
pcie: pcie@2000000000 {
compatible = "microchip,pcie-host-1.0";
#address-cells = <0x3>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>;
reg-names = "cfg", "apb";
clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
clock-names = "fic0", "fic1", "fic3";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <PLIC_INT_FABRIC_F2H_2>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
interrupt-map-mask = <0 0 0 7>;
ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
msi-parent = <&pcie>;
msi-controller;
mchp,axi-m-atr0 = <0x10 0x0>;
status = "disabled";
pcie_intc: legacy-interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
syscontroller: syscontroller {
compatible = "microchip,mpfs-sys-controller";
#address-cells = <1>;
#size-cells = <1>;
mboxes = <&mbox 0>;
};
hwrandom: hwrandom {
compatible = "microchip,mpfs-rng";
#address-cells = <1>;
#size-cells = <1>;
syscontroller = <&syscontroller>;
};
serialnum: serialnum {
compatible = "microchip,mpfs-serial-number";
#address-cells = <1>;
#size-cells = <1>;
syscontroller = <&syscontroller>;
};
fpgadigest: fpgadigest {
compatible = "microchip,mpfs-digest";
#address-cells = <1>;
#size-cells = <1>;
syscontroller = <&syscontroller>;
};
devicecert: cert {
compatible = "microchip,mpfs-device-cert";
#address-cells = <1>;
#size-cells = <1>;
syscontroller = <&syscontroller>;
};
signature: signature {
compatible = "microchip,mpfs-signature";
#address-cells = <1>;
#size-cells = <1>;
syscontroller = <&syscontroller>;
};
};
};
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