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u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3368.h

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rockchip: rk3368: Add clock driver Add driver to setup the various PLLs and peripheral clocks on the RK3368. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-15 09:49:56 +00:00
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
* Author: Andy Yan <andy.yan@rock-chips.com>
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_CRU_RK3368_H
#define _ASM_ARCH_CRU_RK3368_H
#include <common.h>
/* RK3368 clock numbers */
enum rk3368_pll_id {
APLLB,
APLLL,
DPLL,
CPLL,
GPLL,
NPLL,
PLL_COUNT,
};
struct rk3368_cru {
struct rk3368_pll {
unsigned int con0;
unsigned int con1;
unsigned int con2;
unsigned int con3;
} pll[6];
unsigned int reserved[0x28];
unsigned int clksel_con[56];
unsigned int reserved1[8];
unsigned int clkgate_con[25];
unsigned int reserved2[7];
unsigned int glb_srst_fst_val;
unsigned int glb_srst_snd_val;
unsigned int reserved3[0x1e];
unsigned int softrst_con[15];
unsigned int reserved4[0x11];
unsigned int misc_con;
unsigned int glb_cnt_th;
unsigned int glb_rst_con;
unsigned int glb_rst_st;
unsigned int reserved5[0x1c];
unsigned int sdmmc_con[2];
unsigned int sdio0_con[2];
unsigned int sdio1_con[2];
unsigned int emmc_con[2];
};
check_member(rk3368_cru, emmc_con[1], 0x41c);
struct rk3368_clk_priv {
struct rk3368_cru *cru;
};
enum {
/* PLL CON0 */
PLL_NR_SHIFT = 8,
PLL_NR_MASK = GENMASK(13, 8),
PLL_OD_SHIFT = 0,
PLL_OD_MASK = GENMASK(3, 0),
/* PLL CON1 */
PLL_LOCK_STA = BIT(31),
PLL_NF_SHIFT = 0,
PLL_NF_MASK = GENMASK(12, 0),
/* PLL CON2 */
PLL_BWADJ_SHIFT = 0,
PLL_BWADJ_MASK = GENMASK(11, 0),
/* PLL CON3 */
PLL_MODE_SHIFT = 8,
PLL_MODE_MASK = GENMASK(9, 8),
PLL_MODE_SLOW = 0,
PLL_MODE_NORMAL = 1,
PLL_MODE_DEEP_SLOW = 3,
PLL_RESET_SHIFT = 5,
PLL_RESET = 1,
PLL_RESET_MASK = GENMASK(5, 5),
/* CLKSEL12_CON */
MCU_STCLK_DIV_SHIFT = 8,
MCU_STCLK_DIV_MASK = GENMASK(10, 8),
MCU_PLL_SEL_SHIFT = 7,
MCU_PLL_SEL_MASK = BIT(7),
MCU_PLL_SEL_CPLL = 0,
MCU_PLL_SEL_GPLL = 1,
MCU_CLK_DIV_SHIFT = 0,
MCU_CLK_DIV_MASK = GENMASK(4, 0),
rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock To enable the GMAC on the RK3368, we need to set up the clocking appropriately to generate a tx_clk for the MAC. This adds an implementation that implements the use of the <&ext_gmac> clock (i.e. an external 125MHz clock for RGMII provided by the PHY). This is the clock setup used by the boards currently supported by U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7). This includes the change from commit - rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-14 17:57:39 +00:00
/* CLKSEL43_CON */
GMAC_MUX_SEL_EXTCLK = BIT(8),
rockchip: rk3368: Add clock driver Add driver to setup the various PLLs and peripheral clocks on the RK3368. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-15 09:49:56 +00:00
/* CLKSEL51_CON */
MMC_PLL_SEL_SHIFT = 8,
MMC_PLL_SEL_MASK = GENMASK(9, 8),
rockchip: clk: rk3368: implement MMC/SD clock reparenting The original clock support for MMC/SD cards on the RK3368 suffered from a tendency to select a divider less-or-equal to the the one giving the requested clock-rate: this can lead to higher-than-expected (or rather: higher than supported) clock rates for the MMC/SD communiction. This change rewrites the MMC/SD clock generation to: * always generate a clock less-than-or-equal to the requested clock * support reparenting among the CPLL, GPLL and OSC24M parents to generate the highest clock that does not exceed the requested rate In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup always works), we adjust the driver appropriately. This includes the changes from: - rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-04 12:49:38 +00:00
MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT),
MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT),
MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT),
MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT),
rockchip: rk3368: Add clock driver Add driver to setup the various PLLs and peripheral clocks on the RK3368. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-15 09:49:56 +00:00
MMC_CLK_DIV_SHIFT = 0,
MMC_CLK_DIV_MASK = GENMASK(6, 0),
/* SOFTRST1_CON */
MCU_PO_SRST_MASK = BIT(13),
MCU_SYS_SRST_MASK = BIT(12),
rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ On he RK3368, we need to temporarily disable security on the DMA engines during TPL and SPL to allow the MMC host to DMA into DRAM. To do so, we need to reset the two DMA engines, which in turn requires the DMA1_SRST_REQ and DMA2_SRST_REQ constants to refer to the appropriate bits in the CRU. As the ATF correctly initialises security (and only leaves EL3 after doing so), this can not pose a security issue. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-04 12:50:11 +00:00
DMA1_SRST_REQ = BIT(2),
/* SOFTRST4_CON */
DMA2_SRST_REQ = BIT(0),
rockchip: rk3368: Add clock driver Add driver to setup the various PLLs and peripheral clocks on the RK3368. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-15 09:49:56 +00:00
/* GLB_RST_CON */
PMU_GLB_SRST_CTRL_SHIFT = 2,
PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2),
PMU_RST_BY_FST_GLB_SRST = 0,
PMU_RST_BY_SND_GLB_SRST = 1,
PMU_RST_DISABLE = 2,
WDT_GLB_SRST_CTRL_SHIFT = 1,
WDT_GLB_SRST_CTRL_MASK = BIT(1),
WDT_TRIGGER_SND_GLB_SRST = 0,
WDT_TRIGGER_FST_GLB_SRST = 1,
TSADC_GLB_SRST_CTRL_SHIFT = 0,
TSADC_GLB_SRST_CTRL_MASK = BIT(0),
TSADC_TRIGGER_SND_GLB_SRST = 0,
TSADC_TRIGGER_FST_GLB_SRST = 1,
};
#endif
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