2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2005-10-04 21:10:28 +00:00
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/*
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* (C) Copyright 2005
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* ARM Ltd.
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* Peter Pearse, <Peter.Pearse@arm.com>
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* Configuration for ARM Core Modules.
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* No standalonw port yet available
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* - this file is included by both integratorap.h & integratorcp.h
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*/
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#ifndef __ARMCOREMODULE_H
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#define __ARMCOREMODULE_H
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2008-05-20 14:00:29 +00:00
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#define CM_BASE 0x10000000
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2005-10-04 21:10:28 +00:00
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/* CM registers common to all CMs */
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/* Note that observed values after reboot into the ARM Boot Monitor
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have been used as defaults, rather than the POR values */
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2008-05-20 14:00:29 +00:00
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#define OS_CTRL 0x0000000C
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2005-10-04 21:10:28 +00:00
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#define CMMASK_REMAP 0x00000005 /* set remap & led */
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#define CMMASK_RESET 0x00000008
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2008-05-20 14:00:29 +00:00
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#define OS_LOCK 0x00000014
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#define CMVAL_LOCK1 0x0000A000 /* locking value */
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2005-10-04 21:10:28 +00:00
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#define CMVAL_LOCK2 0x0000005F /* locking value */
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#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
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#define OS_SDRAM 0x00000020
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2008-05-20 14:00:29 +00:00
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#define OS_INIT 0x00000024
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2005-10-04 21:10:28 +00:00
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#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
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#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
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#define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */
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#define CMMASK_LE 0xFFFFFFF7 /* little endian */
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#define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */
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/* - observed reset value of */
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/* CM926EJ-S */
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/* CM1136-EJ-S */
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#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
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#endif /* __ARMCOREMODULE_H */
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