2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2015-11-20 12:17:22 +00:00
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/*
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* Copyright 2015 - 2016 Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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2020-05-10 17:40:01 +00:00
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#include <image.h>
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2019-11-14 19:57:46 +00:00
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#include <init.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2015-11-20 12:17:22 +00:00
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#include <spl.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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2015-11-20 12:17:22 +00:00
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#include <asm/io.h>
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#include <asm/spl.h>
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#include <asm/arch/hardware.h>
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2019-12-03 14:02:50 +00:00
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#include <asm/arch/psu_init_gpl.h>
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2015-11-20 12:17:22 +00:00
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#include <asm/arch/sys_proto.h>
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void board_init_f(ulong dummy)
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{
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2017-07-12 11:08:41 +00:00
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board_early_init_f();
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2015-11-20 12:17:22 +00:00
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board_early_init_r();
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}
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2016-08-15 07:41:36 +00:00
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static void ps_mode_reset(ulong mode)
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{
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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udelay(5);
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writel(mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT |
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mode << ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT,
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&crlapb_base->boot_pin_ctrl);
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}
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/*
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* Set default PS_MODE1 which is used for USB ULPI phy reset
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* Also other resets can be connected to this certain pin
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*/
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#ifndef MODE_RESET
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# define MODE_RESET PS_MODE1
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#endif
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2015-11-20 12:17:22 +00:00
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init(void)
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{
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preloader_console_init();
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2016-08-15 07:41:36 +00:00
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ps_mode_reset(MODE_RESET);
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2015-11-20 12:17:22 +00:00
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board_init();
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2019-12-03 14:02:50 +00:00
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psu_post_config_data();
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2015-11-20 12:17:22 +00:00
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}
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#endif
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2019-12-09 12:00:57 +00:00
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = spl_boot_device();
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if (spl_boot_list[0] == BOOT_DEVICE_MMC1)
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spl_boot_list[1] = BOOT_DEVICE_MMC2;
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if (spl_boot_list[0] == BOOT_DEVICE_MMC2)
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spl_boot_list[1] = BOOT_DEVICE_MMC1;
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2020-03-11 14:00:51 +00:00
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spl_boot_list[2] = BOOT_DEVICE_RAM;
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2019-12-09 12:00:57 +00:00
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}
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2015-11-20 12:17:22 +00:00
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u32 spl_boot_device(void)
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{
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u32 reg = 0;
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u8 bootmode;
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2016-08-30 14:17:27 +00:00
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#if defined(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE_ENABLED)
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/* Change default boot mode at run-time */
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2016-10-25 09:43:02 +00:00
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writel(CONFIG_SPL_ZYNQMP_ALT_BOOTMODE << BOOT_MODE_ALT_SHIFT,
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2016-08-30 14:17:27 +00:00
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&crlapb_base->boot_mode);
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#endif
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2015-11-20 12:17:22 +00:00
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reg = readl(&crlapb_base->boot_mode);
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2016-10-25 09:43:02 +00:00
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if (reg >> BOOT_MODE_ALT_SHIFT)
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reg >>= BOOT_MODE_ALT_SHIFT;
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2015-11-20 12:17:22 +00:00
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bootmode = reg & BOOT_MODES_MASK;
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switch (bootmode) {
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case JTAG_MODE:
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return BOOT_DEVICE_RAM;
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#ifdef CONFIG_SPL_MMC_SUPPORT
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2017-04-03 01:44:34 +00:00
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case SD_MODE1:
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2017-03-02 10:02:55 +00:00
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case SD1_LSHFT_MODE: /* not working on silicon v1 */
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2017-04-03 01:44:34 +00:00
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return BOOT_DEVICE_MMC2;
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2015-11-20 12:17:22 +00:00
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case SD_MODE:
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2017-04-03 01:44:34 +00:00
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case EMMC_MODE:
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2015-11-20 12:17:22 +00:00
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return BOOT_DEVICE_MMC1;
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2016-08-19 12:14:52 +00:00
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#endif
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2019-01-17 19:43:02 +00:00
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#ifdef CONFIG_SPL_DFU
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2016-08-19 12:14:52 +00:00
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case USB_MODE:
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return BOOT_DEVICE_DFU;
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2016-10-26 07:24:32 +00:00
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#endif
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#ifdef CONFIG_SPL_SATA_SUPPORT
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case SW_SATA_MODE:
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return BOOT_DEVICE_SATA;
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2017-11-02 08:15:05 +00:00
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#endif
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#ifdef CONFIG_SPL_SPI_SUPPORT
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case QSPI_MODE_24BIT:
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case QSPI_MODE_32BIT:
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return BOOT_DEVICE_SPI;
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2015-11-20 12:17:22 +00:00
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#endif
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default:
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printf("Invalid Boot Mode:0x%x\n", bootmode);
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break;
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}
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return 0;
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}
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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return 0;
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}
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#endif
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