2020-12-16 07:51:53 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <log.h>
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#include <asm/io.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <dt-bindings/clock/g12a-aoclkc.h>
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#include "clk_meson.h"
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struct meson_clk {
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struct regmap *map;
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};
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#define AO_CLK_GATE0 0x4c
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#define AO_SAR_CLK 0x90
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static struct meson_gate gates[] = {
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MESON_GATE(CLKID_AO_SAR_ADC, AO_CLK_GATE0, 8),
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MESON_GATE(CLKID_AO_SAR_ADC_CLK, AO_SAR_CLK, 8),
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};
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static int meson_set_gate(struct clk *clk, bool on)
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{
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struct meson_clk *priv = dev_get_priv(clk->dev);
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struct meson_gate *gate;
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gate = &gates[clk->id];
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regmap_update_bits(priv->map, gate->reg,
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BIT(gate->bit), on ? BIT(gate->bit) : 0);
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return 0;
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}
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static int meson_clk_enable(struct clk *clk)
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{
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return meson_set_gate(clk, true);
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}
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static int meson_clk_disable(struct clk *clk)
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{
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return meson_set_gate(clk, false);
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}
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static int meson_clk_probe(struct udevice *dev)
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{
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struct meson_clk *priv = dev_get_priv(dev);
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2021-01-12 20:46:52 +00:00
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priv->map = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev)));
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2020-12-16 07:51:53 +00:00
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if (IS_ERR(priv->map))
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return PTR_ERR(priv->map);
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return 0;
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}
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2022-04-24 08:21:56 +00:00
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static int meson_clk_request(struct clk *clk)
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{
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if (clk->id >= ARRAY_SIZE(gates))
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return -ENOENT;
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return 0;
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}
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2020-12-16 07:51:53 +00:00
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static struct clk_ops meson_clk_ops = {
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.disable = meson_clk_disable,
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.enable = meson_clk_enable,
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2022-04-24 08:21:56 +00:00
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.request = meson_clk_request,
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2020-12-16 07:51:53 +00:00
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};
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static const struct udevice_id meson_clk_ids[] = {
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{ .compatible = "amlogic,meson-g12a-aoclkc" },
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{ }
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};
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2022-04-24 08:21:55 +00:00
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U_BOOT_DRIVER(meson_clk_g12a_ao) = {
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2020-12-16 07:51:53 +00:00
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.name = "meson_clk_g12a_ao",
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.id = UCLASS_CLK,
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.of_match = meson_clk_ids,
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2021-01-12 20:46:52 +00:00
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.priv_auto = sizeof(struct meson_clk),
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2020-12-16 07:51:53 +00:00
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.ops = &meson_clk_ops,
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.probe = meson_clk_probe,
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};
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