2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2017-05-14 19:42:27 +00:00
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/*
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* Board-specific sbf ddr/sdram init.
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*
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* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
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*/
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#include <config.h>
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.global sbf_dram_init
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.text
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sbf_dram_init:
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/* Dram Initialization a1, a2, and d0 */
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/* mscr sdram */
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move.l #0xFC0A4074, %a1
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move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
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nop
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/* SDRAM Chip 0 and 1 */
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move.l #0xFC0B8110, %a1
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move.l #0xFC0B8114, %a2
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/* calculate the size */
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move.l #0x13, %d1
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move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
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#ifdef CONFIG_SYS_SDRAM_BASE1
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lsr.l #1, %d2
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#endif
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dramsz_loop:
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lsr.l #1, %d2
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add.l #1, %d1
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cmp.l #1, %d2
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bne dramsz_loop
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#ifdef CONFIG_SYS_NAND_BOOT
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beq asm_nand_chk_status
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#endif
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/* SDRAM Chip 0 and 1 */
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move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
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or.l %d1, (%a1)
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#ifdef CONFIG_SYS_SDRAM_BASE1
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move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
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or.l %d1, (%a2)
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#endif
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nop
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/* dram cfg1 and cfg2 */
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move.l #0xFC0B8008, %a1
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move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
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nop
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move.l #0xFC0B800C, %a2
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move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
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nop
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move.l #0xFC0B8000, %a1 /* Mode */
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move.l #0xFC0B8004, %a2 /* Ctrl */
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/* Issue PALL */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
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nop
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/* Issue LEMR */
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move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
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nop
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move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
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nop
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move.l #1000, %d1
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bsr asm_delay
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/* Issue PALL */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
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nop
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/* Perform two refresh cycles */
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move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
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nop
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move.l %d0, (%a2)
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move.l %d0, (%a2)
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nop
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move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
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nop
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move.l #500, %d1
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bsr asm_delay
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move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
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and.l #0x7FFFFFFF, %d1
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or.l #0x10000C00, %d1
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move.l %d1, (%a2)
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nop
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move.l #2000, %d1
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bsr asm_delay
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rts
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