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riscv: kconfig: Normalize architecture name spelling It's RISC-V that is the official name, not RISCV. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>
2018-09-26 13:55:06 +00:00
menu "RISC-V architecture"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
depends on RISCV
config SYS_ARCH
default "riscv"
choice
prompt "Target select"
optional
riscv: Rename Andes cpu and board names The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-14 12:42:49 +00:00
config TARGET_AE350
bool "Support ae350"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
riscv: Add Microchip MPFS Icicle board support This patch adds Microchip MPFS Icicle board support. For now, NS16550 serial driver is only enabled. The Microchip MPFS Icicle defconfig by default builds U-Boot for M-Mode with SMP support. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-05-28 10:17:51 +00:00
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
riscv: Add QEMU virt board support This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-09-26 13:55:21 +00:00
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
riscv: sifive: Rename fu540 board to unleashed In preparation to add SiFive Unmatched board support, let's rename the existing fu540 board to unleashed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-03-17 03:10:58 +00:00
config TARGET_SIFIVE_UNLEASHED
bool "Support SiFive Unleashed Board"
riscv: Add SiFive FU540 board support This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-25 08:15:19 +00:00
board: sifive: add HiFive Unmatched board support Add defconfig and board support for HiFive Unmatched. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-27 13:52:13 +00:00
config TARGET_SIFIVE_UNMATCHED
bool "Support SiFive Unmatched Board"
Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16. Introduce select statements for other architectures based on current usage. For MIPS, we take the existing arch-specific symbol and migrate to the generic symbol. This lets us remove a little bit of otherwise unused code. Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Leo <ycliang@andestech.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-26 15:47:59 +00:00
select SYS_CACHE_SHIFT_6
board: sifive: add HiFive Unmatched board support Add defconfig and board support for HiFive Unmatched. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-27 13:52:13 +00:00
board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-03-29 03:42:20 +00:00
config TARGET_STARFIVE_VISIONFIVE2
bool "Support StarFive VisionFive2 Board"
riscv: t-head: licheepi4a: initial support added Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial console are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot. Reviewed-by: Wei Fu <wefu@redhat.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
2023-07-08 11:24:32 +00:00
config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"
select SYS_CACHE_SHIFT_6
riscv: Add Sipeed Maix support The Sipeed Maix series is a collection of boards built around the RISC-V Kendryte K210 processor. This processor contains several peripherals to accelerate neural network processing and other "ai" tasks. This includes a "KPU" neural network processor, an audio processor supporting beamforming reception, and a digital video port supporting capture and output at VGA resolution. Other peripherals include 8M of sram (accessible with and without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; on-board usb-serial bridges; ports for cameras, displays, and sd cards; and ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly similar. Documentation for Maix boards is located at <http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is located at <https://kendryte.com/downloads/>. However, hardware details are rather lacking, so most technical reference has been taken from the standalone sdk located at <https://github.com/kendryte/kendryte-standalone-sdk>. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-06-24 10:41:25 +00:00
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16. Introduce select statements for other architectures based on current usage. For MIPS, we take the existing arch-specific symbol and migrate to the generic symbol. This lets us remove a little bit of otherwise unused code. Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Leo <ycliang@andestech.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-26 15:47:59 +00:00
select SYS_CACHE_SHIFT_6
riscv: Add Sipeed Maix support The Sipeed Maix series is a collection of boards built around the RISC-V Kendryte K210 processor. This processor contains several peripherals to accelerate neural network processing and other "ai" tasks. This includes a "KPU" neural network processor, an audio processor supporting beamforming reception, and a digital video port supporting capture and output at VGA resolution. Other peripherals include 8M of sram (accessible with and without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; on-board usb-serial bridges; ports for cameras, displays, and sd cards; and ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly similar. Documentation for Maix boards is located at <http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is located at <https://kendryte.com/downloads/>. However, hardware details are rather lacking, so most technical reference has been taken from the standalone sdk located at <https://github.com/kendryte/kendryte-standalone-sdk>. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-06-24 10:41:25 +00:00
board: riscv: add openpiton-riscv64 SoC support This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-01 04:54:19 +00:00
config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
endchoice
CONFIG_SYS_[DI]CACHE_OFF: convert to Kconfig CONFIG_SYS_[DI]CACHE_OFF had been partially converted to Kconfig parameters; only for the ARC architecture. This patch turns these two parameters into Kconfig items everywhere else they are found. All of the include/configs/* and defconfig changes in this patch are for arm machines only. The Kconfig changes for arc, nds32, riscv, and xtensa have been included since these symbols are found in code under arch/{arc,nds32,riscv,xtensa}, however, no currently-defined include/configs/* or defconfigs for these architectures exist which include these symbols. These results have been confirmed with tools/moveconfig.py. Acked-by: Alexey Brodkin <abrodkin@snopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Re-migrate for a few more boards] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-03 13:40:59 +00:00
config SYS_ICACHE_OFF
bool "Do not enable icache"
help
Do not enable instruction cache in U-Boot.
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-03 13:41:00 +00:00
config SPL_SYS_ICACHE_OFF
bool "Do not enable icache in SPL"
depends on SPL
default SYS_ICACHE_OFF
help
Do not enable instruction cache in SPL.
CONFIG_SYS_[DI]CACHE_OFF: convert to Kconfig CONFIG_SYS_[DI]CACHE_OFF had been partially converted to Kconfig parameters; only for the ARC architecture. This patch turns these two parameters into Kconfig items everywhere else they are found. All of the include/configs/* and defconfig changes in this patch are for arm machines only. The Kconfig changes for arc, nds32, riscv, and xtensa have been included since these symbols are found in code under arch/{arc,nds32,riscv,xtensa}, however, no currently-defined include/configs/* or defconfigs for these architectures exist which include these symbols. These results have been confirmed with tools/moveconfig.py. Acked-by: Alexey Brodkin <abrodkin@snopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Re-migrate for a few more boards] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-03 13:40:59 +00:00
config SYS_DCACHE_OFF
bool "Do not enable dcache"
help
Do not enable data cache in U-Boot.
CONFIG_SPL_SYS_[DI]CACHE_OFF: add While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-05-03 13:41:00 +00:00
config SPL_SYS_DCACHE_OFF
bool "Do not enable dcache in SPL"
depends on SPL
default SYS_DCACHE_OFF
help
Do not enable data cache in SPL.
riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE Add a Kconfig item to allow SPL to clear stack/GD/malloc area before using them. Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-09 13:11:31 +00:00
config SPL_ZERO_MEM_BEFORE_USE
bool "Zero memory before use"
depends on SPL
default n
help
Zero stack/GD/malloc area in SPL before using them, this is needed for
Sifive core devices that uses L2 cache to store SPL.
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-07 01:34:06 +00:00
# board-specific options below
riscv: Rename Andes cpu and board names The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-14 12:42:49 +00:00
source "board/AndesTech/ae350/Kconfig"
riscv: Add QEMU virt board support This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-09-26 13:55:21 +00:00
source "board/emulation/qemu-riscv/Kconfig"
riscv: Add Microchip MPFS Icicle board support This patch adds Microchip MPFS Icicle board support. For now, NS16550 serial driver is only enabled. The Microchip MPFS Icicle defconfig by default builds U-Boot for M-Mode with SMP support. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-05-28 10:17:51 +00:00
source "board/microchip/mpfs_icicle/Kconfig"
riscv: sifive: Rename fu540 board to unleashed In preparation to add SiFive Unmatched board support, let's rename the existing fu540 board to unleashed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-03-17 03:10:58 +00:00
source "board/sifive/unleashed/Kconfig"
board: sifive: add HiFive Unmatched board support Add defconfig and board support for HiFive Unmatched. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-27 13:52:13 +00:00
source "board/sifive/unmatched/Kconfig"
riscv: t-head: licheepi4a: initial support added Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's TH1520 SoC, only minimal device tree and serial console are enabled, so it's capable of chain booting from T-HEAD's vendor u-boot. Reviewed-by: Wei Fu <wefu@redhat.com> Signed-off-by: Yixun Lan <dlan@gentoo.org>
2023-07-08 11:24:32 +00:00
source "board/thead/th1520_lpi4a/Kconfig"
board: riscv: add openpiton-riscv64 SoC support This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-01 04:54:19 +00:00
source "board/openpiton/riscv64/Kconfig"
riscv: Add Sipeed Maix support The Sipeed Maix series is a collection of boards built around the RISC-V Kendryte K210 processor. This processor contains several peripherals to accelerate neural network processing and other "ai" tasks. This includes a "KPU" neural network processor, an audio processor supporting beamforming reception, and a digital video port supporting capture and output at VGA resolution. Other peripherals include 8M of sram (accessible with and without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256 accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix peripherals vary, but include spi flash; on-board usb-serial bridges; ports for cameras, displays, and sd cards; and ESP32 chips. Currently, only the Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly similar. Documentation for Maix boards is located at <http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is located at <https://kendryte.com/downloads/>. However, hardware details are rather lacking, so most technical reference has been taken from the standalone sdk located at <https://github.com/kendryte/kendryte-standalone-sdk>. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-06-24 10:41:25 +00:00
source "board/sipeed/maix/Kconfig"
board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-03-29 03:42:20 +00:00
source "board/starfive/visionfive2/Kconfig"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-07 01:34:06 +00:00
# platform-specific options below
riscv: Rename Andes cpu and board names The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2023-02-14 12:42:49 +00:00
source "arch/riscv/cpu/andesv5/Kconfig"
riscv: cpu: fu540: Add support for cpu fu540 Add SiFive fu540 cpu to support RISC-V arch Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-29 06:03:34 +00:00
source "arch/riscv/cpu/fu540/Kconfig"
riscv: cpu: fu740: Add support for cpu fu740 Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-27 13:52:07 +00:00
source "arch/riscv/cpu/fu740/Kconfig"
riscv: Rename cpu/qemu to cpu/generic The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-25 08:14:10 +00:00
source "arch/riscv/cpu/generic/Kconfig"
board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to Kconfig Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-03-29 03:42:20 +00:00
source "arch/riscv/cpu/jh7110/Kconfig"
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
2018-11-07 01:34:06 +00:00
# architecture-specific options below
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
choice
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:12 +00:00
prompt "Base ISA"
default ARCH_RV32I
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:12 +00:00
config ARCH_RV32I
bool "RV32I"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
select 32BIT
help
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:12 +00:00
Choose this option to target the RV32I base integer instruction set.
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:12 +00:00
config ARCH_RV64I
bool "RV64I"
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
select 64BIT
riscv: select CONFIG_PHYS_64BIT on RV64I systems CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:13 +00:00
select PHYS_64BIT
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
help
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2018-11-22 10:26:12 +00:00
Choose this option to target the RV64I base integer instruction set.
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
endchoice
riscv: add Kconfig entries for the code model RISC-V has two code models, medium low (medlow) and medium any (medany). Medlow limits addressable memory to a single 2 GiB range between the absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory to any single 2 GiB address range. By default, medlow is selected for U-Boot on both 32-bit and 64-bit systems. The -mcmodel compiler flag is selected according to the Kconfig configuration. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> [bmeng: adjust to make medlow the default code model for U-Boot] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:23 +00:00
choice
prompt "Code Model"
default CMODEL_MEDLOW
config CMODEL_MEDLOW
bool "medium low code model"
help
U-Boot and its statically defined symbols must lie within a single 2 GiB
address range and must lie between absolute addresses -2 GiB and +2 GiB.
config CMODEL_MEDANY
bool "medium any code model"
help
U-Boot and its statically defined symbols must be within any single 2 GiB
address range.
endchoice
riscv: Introduce a Kconfig option for machine mode So far we have a Kconfig option for supervisor mode. This adds an option for the machine mode. Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-12-12 14:12:29 +00:00
choice
prompt "Run Mode"
default RISCV_MMODE
config RISCV_MMODE
bool "Machine"
help
Choose this option to build U-Boot for RISC-V M-Mode.
config RISCV_SMODE
bool "Supervisor"
help
Choose this option to build U-Boot for RISC-V S-Mode.
endchoice
riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:43 +00:00
choice
prompt "SPL Run Mode"
default SPL_RISCV_MMODE
depends on SPL
config SPL_RISCV_MMODE
bool "Machine"
help
Choose this option to build U-Boot SPL for RISC-V M-Mode.
config SPL_RISCV_SMODE
bool "Supervisor"
help
Choose this option to build U-Boot SPL for RISC-V S-Mode.
endchoice
riscv: add Kconfig entries for the C and A ISA extensions Add Kconfig entries for the C (compressed instructions) and A (atomic instructions) ISA extensions. Only the C ISA extension is selectable. This matches the configuration in Linux. The Kconfig entries are not used yet. A follow-up patch will select the appropriate compiler flags based on the Kconfig configuration. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-22 10:26:14 +00:00
config RISCV_ISA_C
bool "Emit compressed instructions"
default y
help
Adds "C" to the ISA subsets that the toolchain is allowed to emit
when building U-Boot, which results in compressed instructions in the
U-Boot binary.
riscv: support building double-float modules The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a compiled for double-float. To link to it we have to adjust how we build U-Boot. As U-Boot actually does not use floating point at all this should not make a significant difference for the produced binaries. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-10-12 12:59:51 +00:00
config RISCV_ISA_F
bool "Standard extension for Single-Precision Floating Point"
default y
help
Adds "F" to the ISA string passed to the compiler.
config RISCV_ISA_D
bool "Standard extension for Double-Precision Floating Point"
depends on RISCV_ISA_F
default y
help
Adds "D" to the ISA string passed to the compiler and changes the
riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
lp64d.
riscv: add Kconfig entries for the C and A ISA extensions Add Kconfig entries for the C (compressed instructions) and A (atomic instructions) ISA extensions. Only the C ISA extension is selectable. This matches the configuration in Linux. The Kconfig entries are not used yet. A follow-up patch will select the appropriate compiler flags based on the Kconfig configuration. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-11-22 10:26:14 +00:00
config RISCV_ISA_A
def_bool y
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
config 32BIT
bool
config 64BIT
bool
riscv: Add DMA 64-bit address support dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-01-15 02:50:35 +00:00
config DMA_ADDR_T_64BIT
bool
default y if 64BIT
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-06-21 15:11:46 +00:00
config RISCV_ACLINT
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:30 +00:00
bool
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-05-11 12:04:12 +00:00
depends on RISCV_MMODE
riscv: clint: Update the sifive clint ipi driver to support aclint This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint ipi driver to support ACLINT mswi device, by checking the per-driver data field of the ACLINT mtimer driver to determine whether a syscon based approach needs to be taken to get the base address of the ACLINT mswi device. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-06-21 15:11:45 +00:00
select REGMAP
select SYSCON
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-05-11 12:04:12 +00:00
help
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-06-21 15:11:46 +00:00
The RISC-V ACLINT block holds memory-mapped control and status registers
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-05-11 12:04:12 +00:00
associated with software and timer interrupts.
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-06-21 15:11:46 +00:00
config SPL_RISCV_ACLINT
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-05-11 12:04:12 +00:00
bool
depends on SPL_RISCV_MMODE
riscv: clint: Update the sifive clint ipi driver to support aclint This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint ipi driver to support ACLINT mswi device, by checking the per-driver data field of the ACLINT mtimer driver to determine whether a syscon based approach needs to be taken to get the base address of the ACLINT mswi device. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-06-21 15:11:45 +00:00
select SPL_REGMAP
select SPL_SYSCON
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:30 +00:00
help
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-06-21 15:11:46 +00:00
The RISC-V ACLINT block holds memory-mapped control and status registers
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:30 +00:00
associated with software and timer interrupts.
riscv: lib: implement enable_caches for sifive cache The enable_caches is a generic hook for architecture-implemented, we define this function to enable composable cache of sifive platforms. In sifive_cache, it invokes the generic cache_enable interface of cache uclass to execute the relative implementation in SiFive ccache driver. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-01 07:01:41 +00:00
config SIFIVE_CACHE
bool
help
This enables the operations to configure SiFive cache
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-25 15:03:50 +00:00
config ANDES_PLICSW
riscv: Add a SYSCON driver for Andestech's PLIC The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:39 +00:00
bool
riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:43 +00:00
depends on RISCV_MMODE || SPL_RISCV_MMODE
riscv: Add a SYSCON driver for Andestech's PLIC The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:39 +00:00
select REGMAP
select SYSCON
riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:43 +00:00
select SPL_REGMAP if SPL
select SPL_SYSCON if SPL
riscv: Add a SYSCON driver for Andestech's PLIC The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:39 +00:00
help
riscv: Rename Andes PLIC to PLICSW As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-25 15:03:50 +00:00
The Andes PLICSW block holds memory-mapped claim and pending
registers associated with software interrupt.
riscv: Add a SYSCON driver for Andestech's PLIC The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:39 +00:00
riscv: add infrastructure for calling functions on other harts Harts on RISC-V boot independently, U-Boot is responsible for managing them. Functions are called on other harts with smp_call_function(), which sends inter-processor interrupts (IPIs) to all other available harts. Available harts are those marked as available in the device tree and present in the available_harts mask stored in global data. The available_harts mask is used to register all harts that have entered U-Boot. Functions are specified with their address and two function arguments (argument 2 and 3). The first function argument is always the hart ID of the hart calling the function. On the other harts, the IPI interrupt handler handle_ipi() must be called on software interrupts to handle the request and call the specified function. Functions are stored in the ipi_data data structure. Every hart has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-17 18:28:32 +00:00
config SMP
bool "Symmetric Multi-Processing"
riscv: Add SMP Kconfig option dependency for U-Boot proper U-Boot proper running in S-mode only need SMP support when using SBI v0.1. With SBI v0.2 HSM extension, it does not need implement multicore boot in U-Boot proper. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-16 15:09:31 +00:00
depends on SBI_V01 || !RISCV_SMODE
riscv: add infrastructure for calling functions on other harts Harts on RISC-V boot independently, U-Boot is responsible for managing them. Functions are called on other harts with smp_call_function(), which sends inter-processor interrupts (IPIs) to all other available harts. Available harts are those marked as available in the device tree and present in the available_harts mask stored in global data. The available_harts mask is used to register all harts that have entered U-Boot. Functions are specified with their address and two function arguments (argument 2 and 3). The first function argument is always the hart ID of the hart calling the function. On the other harts, the IPI interrupt handler handle_ipi() must be called on software interrupts to handle the request and call the specified function. Functions are stored in the ipi_data data structure. Every hart has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-17 18:28:32 +00:00
help
This enables support for systems with more than one CPU. If
you say N here, U-Boot will run on single and multiprocessor
machines, but will use only one CPU of a multiprocessor
machine. If you say Y here, U-Boot will run on many, but not
all, single processor machines.
riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL With SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards. For U-Boot running in SPL, SMP can be turned on, while in U-Boot proper, SMP can be optionally turned off if using SBI v0.2 HSM. Introduce a new SPL_SMP Kconfig option to support this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-16 15:09:30 +00:00
config SPL_SMP
bool "Symmetric Multi-Processing in SPL"
depends on SPL && SPL_RISCV_MMODE
default y
help
This enables support for systems with more than one CPU in SPL.
If you say N here, U-Boot SPL will run on single and multiprocessor
machines, but will use only one CPU of a multiprocessor
machine. If you say Y here, U-Boot SPL will run on many, but not
all, single processor machines.
riscv: add infrastructure for calling functions on other harts Harts on RISC-V boot independently, U-Boot is responsible for managing them. Functions are called on other harts with smp_call_function(), which sends inter-processor interrupts (IPIs) to all other available harts. Available harts are those marked as available in the device tree and present in the available_harts mask stored in global data. The available_harts mask is used to register all harts that have entered U-Boot. Functions are specified with their address and two function arguments (argument 2 and 3). The first function argument is always the hart ID of the hart calling the function. On the other harts, the IPI interrupt handler handle_ipi() must be called on software interrupts to handle the request and call the specified function. Functions are stored in the ipi_data data structure. Every hart has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-17 18:28:32 +00:00
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL With SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards. For U-Boot running in SPL, SMP can be turned on, while in U-Boot proper, SMP can be optionally turned off if using SBI v0.2 HSM. Introduce a new SPL_SMP Kconfig option to support this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-16 15:09:30 +00:00
depends on SMP || SPL_SMP
riscv: add infrastructure for calling functions on other harts Harts on RISC-V boot independently, U-Boot is responsible for managing them. Functions are called on other harts with smp_call_function(), which sends inter-processor interrupts (IPIs) to all other available harts. Available harts are those marked as available in the device tree and present in the available_harts mask stored in global data. The available_harts mask is used to register all harts that have entered U-Boot. Functions are specified with their address and two function arguments (argument 2 and 3). The first function argument is always the hart ID of the hart calling the function. On the other harts, the IPI interrupt handler handle_ipi() must be called on software interrupts to handle the request and call the specified function. Functions are stored in the ipi_data data structure. Every hart has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-17 18:28:32 +00:00
default 8
help
On multiprocessor machines, U-Boot sets up a stack for each CPU.
Stack memory is pre-allocated. U-Boot must therefore know the
maximum number of CPUs that may be present.
riscv: Add basic support for SBI v0.2 The SBI v0.2 introduces a base extension which is backward compatible with v0.1. Implement all helper functions and minimum required SBI calls from v0.2 for now. All other base extension function will be added later as per need. As v0.2 calling convention is backward compatible with v0.1, remove the v0.1 helper functions and just use v0.2 calling convention. Add a new Kconfig options CONFIG_SBI for the new SBI v0.2 codes, and let CONFIG_SBI_IPI depend on it. This commit is inspired from Linux kernel patch: https://patchwork.kernel.org/patch/11407363/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-03-10 02:35:28 +00:00
config SBI
bool
default y if RISCV_SMODE || SPL_RISCV_SMODE
riscv: Add Kconfig option for SBI v0.2 SBI v0.2 is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-16 15:09:32 +00:00
choice
prompt "SBI support"
riscv: Make SBI v0.2 the default SBI version To work with latest OpenSBI release (v0.7 or above) that has the HSM extension support, select the SBI v0.2 support by default. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-16 15:09:33 +00:00
default SBI_V02
riscv: Add Kconfig option for SBI v0.2 SBI v0.2 is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-16 15:09:32 +00:00
riscv: Introduce a new config for SBI v0.1 We now have SBI v0.2 which is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. Introduce a new config and move all SBI v0.1 code under that config. This allows to implement the new replacement SBI extensions cleanly and remove v0.1 extensions easily in future. Currently, the config is enabled by default. Once all M-mode software, with v0.1, is no longer in use, this config option and all relevant code can be easily removed. This commit is inspired from Linux kernel patch: https://patchwork.kernel.org/patch/11407361/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-03-10 02:35:30 +00:00
config SBI_V01
bool "SBI v0.1 support"
depends on SBI
help
This config allows kernel to use SBI v0.1 APIs. This will be
deprecated in future once legacy M-mode software are no longer in use.
riscv: Add Kconfig option for SBI v0.2 SBI v0.2 is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-16 15:09:32 +00:00
config SBI_V02
riscv: clarify meaning of CONFIG_SBI_V02 Describe that CONFIG_SBI_V02=y does not mean SBI specification v0.2 but v0.2 or later. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-08 14:53:12 +00:00
bool "SBI v0.2 or later support"
riscv: Add Kconfig option for SBI v0.2 SBI v0.2 is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-16 15:09:32 +00:00
depends on SBI
help
riscv: clarify meaning of CONFIG_SBI_V02 Describe that CONFIG_SBI_V02=y does not mean SBI specification v0.2 but v0.2 or later. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-08 14:53:12 +00:00
The SBI specification introduced the concept of extensions in version
v0.2. With this configuration option U-Boot can detect and use SBI
extensions. With the HSM extension introduced in SBI 0.2, only a
single hart needs to boot and enter the operating system. The booting
hart can bring up secondary harts one by one afterwards.
riscv: Add Kconfig option for SBI v0.2 SBI v0.2 is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-16 15:09:32 +00:00
riscv: clarify meaning of CONFIG_SBI_V02 Describe that CONFIG_SBI_V02=y does not mean SBI specification v0.2 but v0.2 or later. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-11-08 14:53:12 +00:00
Choose this option if OpenSBI release v0.7 or above is used together
riscv: Add Kconfig option for SBI v0.2 SBI v0.2 is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-16 15:09:32 +00:00
with U-Boot.
endchoice
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-17 18:28:34 +00:00
config SBI_IPI
bool
riscv: Add basic support for SBI v0.2 The SBI v0.2 introduces a base extension which is backward compatible with v0.1. Implement all helper functions and minimum required SBI calls from v0.2 for now. All other base extension function will be added later as per need. As v0.2 calling convention is backward compatible with v0.1, remove the v0.1 helper functions and just use v0.2 calling convention. Add a new Kconfig options CONFIG_SBI for the new SBI v0.2 codes, and let CONFIG_SBI_IPI depend on it. This commit is inspired from Linux kernel patch: https://patchwork.kernel.org/patch/11407363/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-03-10 02:35:28 +00:00
depends on SBI
riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:43 +00:00
default y if RISCV_SMODE || SPL_RISCV_SMODE
riscv: implement IPI platform functions using SBI The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-17 18:28:34 +00:00
depends on SMP
riscv: Introduce CONFIG_XIP to support booting from flash When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-30 05:49:33 +00:00
config XIP
bool "XIP mode"
help
XIP (eXecute In Place) is a method for executing code directly
from a NOR flash memory without copying the code to ram.
Say yes here if U-Boot boots from flash directly.
spl: introduce SPL_XIP to config U-Boot and SPL don't necessary share the same location, so we might end with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory. In case of non XIP boot mode, we rely on such variables as "hart_lottery" and "available_harts_lock" which we use as atomics. The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes. This adds an option special for SPL to behave it in XIP manner and we don't use hart_lottery and available_harts_lock, during start proccess. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-09-02 08:47:39 +00:00
config SPL_XIP
bool "Enable XIP mode for SPL"
help
If SPL starts in read-only memory (XIP for example) then we shouldn't
rely on lock variables (for example hart_lottery and available_harts_lock),
this affects only SPL, other stages should proceed as non-XIP.
riscv: Introduce AVAILABLE_HARTS In SMP all harts will register themself in available_hart during start up. Then main hart will send IPI to other harts according to this variables. But this mechanism may not guarantee that all other harts can jump to next stage. When main hart is sending IPI to other hart according to available_harts, but other harts maybe still not finish the registration. Then the SMP booting will miss some harts finally. So let it become an option and it will be enabled by default. Please refer to the discussion: https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-09-21 06:34:54 +00:00
config AVAILABLE_HARTS
bool "Send IPI by available harts"
default y
help
By default, IPI sending mechanism will depend on available_harts.
If disable this, it will send IPI by CPUs node numbers of device tree.
riscv: Add option to print registers on exception When debugging, it can be helpful to see more information about an unhandled exception. This patch adds an option to view the registers at the time of the trap, similar to the linux output on a kernel panic. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-25 05:27:44 +00:00
config SHOW_REGS
bool "Show registers on unhandled exception"
riscv: Add option to support RISC-V privileged spec 1.9 Some older processors (notably the Kendryte K210) use an older version of the RISC-V privileged specification. The primary changes between the old and new are in virtual memory, and in the merging of three separate counter enable CSRs. Using the new CSR on an old processor causes an illegal instruction exception. This patch adds an option to use the old CSRs instead of the new one. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-24 10:41:19 +00:00
config RISCV_PRIV_1_9
bool "Use version 1.9 of the RISC-V priviledged specification"
help
Older versions of the RISC-V priviledged specification had
separate counter enable CSRs for each privilege mode. Writing
to the unified mcounteren CSR on a processor implementing the
old specification will result in an illegal instruction
exception. In addition to counter CSR changes, the way virtual
memory is configured was also changed.
riscv: add support for multi-hart systems On RISC-V, all harts boot independently. To be able to run on a multi-hart system, U-Boot must be extended with the functionality to manage all harts in the system. All harts entering U-Boot are registered in the available_harts mask stored in global data. A hart lottery system as used in the Linux kernel selects the hart U-Boot runs on. All other harts are halted. U-Boot can delegate functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-17 18:28:37 +00:00
config STACK_SIZE_SHIFT
int
riscv: increase stack size to avoid a stack overflow during distro boot This fixes a problem, where booting Linux using distro boot will sometimes lead to an invalid instruction exception on the main hart. The secondary harts are not affected and boot Linux successfully. The root cause of this problem is a stack overflow on the main hart. With distro boot, the current default stack size of 8KiB on RISC-V is not sufficient and will cause a stack overflow. The stacks are allocated sequentially. In the case of a stack overflow the stack of the main hart can reach into that of another hart and be corrupted. The stack overflow previously did not cause any problems, because only stack frames, which are not used anymore since the hart enters Linux, were corrupted. Starting with GCC 9, the stack usage has decreased. Now, only the most recent stack frame overflows into the stack of a secondary hart and is corrupted. The illegal instruction exception is caused by the secondary hart overwriting the return address in the stack frame of the main hart with an address that does not include valid code. Increase the default stack size of each hart to 16KiB to avoid this problem. Reported-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Rick Chen <rick@andestech.com>
2019-10-20 18:53:47 +00:00
default 14
riscv: add support for multi-hart systems On RISC-V, all harts boot independently. To be able to run on a multi-hart system, U-Boot must be extended with the functionality to manage all harts in the system. All harts entering U-Boot are registered in the available_harts mask stored in global data. A hart lottery system as used in the Linux kernel selects the hart U-Boot runs on. All other harts are halted. U-Boot can delegate functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-17 18:28:37 +00:00
riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the reserved memory node for PMP protected memory regions. All RISC-V boards need to copy the reserved memory node from the device tree provided by the firmware to the device tree used by U-Boot. Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-06-26 01:16:08 +00:00
config OF_BOARD_FIXUP
riscv: Only enable OF_BOARD_FIXUP for S-Mode It is unsafe to enable OF_BOARD_FIXUP only based on OF_SEPARATE. OF_SEPARATE may indicate that the user wishes U-Boot to use a different device tree than one obtained via OF_PRIOR_STAGE. However, OF_SEPARATE may also indicate that the device tree which would be obtained via OF_PRIOR_STAGE is invalid, nonexistant, or otherwise unusable. In this latter case, enabling OF_BOARD_FIXUP will result in corruption of the device tree. To remedy this, only enable OF_BOARD_FIXUP if U-Boot is configured for S-Mode. Fixes: 1c17e55594a394ced7de88d91be294eaf8c564c1 Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-09-05 13:22:11 +00:00
default y if OF_SEPARATE && RISCV_SMODE
riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the reserved memory node for PMP protected memory regions. All RISC-V boards need to copy the reserved memory node from the device tree provided by the firmware to the device tree used by U-Boot. Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-06-26 01:16:08 +00:00
riscv: Group assembly optimized implementation of memory routines into a submenu Currently all assembly optimized implementation of memory routines show up at the top level of the RISC-V architecture Kconfig menu. Let's group them together into a submenu. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-13 08:46:18 +00:00
menu "Use assembly optimized implementation of memory routines"
riscv: assembler versions of memcpy, memmove, memset Provide optimized versions of memcpy(), memmove(), memset() copied from the Linux kernel. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-03-27 11:37:04 +00:00
config USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy"
default y
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for SPL"
default y if USE_ARCH_MEMCPY
depends on SPL
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for TPL"
default y if USE_ARCH_MEMCPY
depends on TPL
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
but may increase the binary size.
config USE_ARCH_MEMMOVE
bool "Use an assembly optimized implementation of memmove"
default y
help
Enable the generation of an optimized version of memmove.
Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMMOVE
bool "Use an assembly optimized implementation of memmove for SPL"
default y if USE_ARCH_MEMCPY
depends on SPL
help
Enable the generation of an optimized version of memmove.
Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMMOVE
bool "Use an assembly optimized implementation of memmove for TPL"
default y if USE_ARCH_MEMCPY
depends on TPL
help
Enable the generation of an optimized version of memmove.
Such an implementation may be faster under some conditions
but may increase the binary size.
config USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset"
default y
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for SPL"
default y if USE_ARCH_MEMSET
depends on SPL
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for TPL"
default y if USE_ARCH_MEMSET
depends on TPL
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
but may increase the binary size.
riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:52 +00:00
endmenu
riscv: Group assembly optimized implementation of memory routines into a submenu Currently all assembly optimized implementation of memory routines show up at the top level of the RISC-V architecture Kconfig menu. Let's group them together into a submenu. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-13 08:46:18 +00:00
endmenu
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