2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2015-08-30 22:55:34 +00:00
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/*
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* Copyright (C) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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2023-03-13 00:30:57 +00:00
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#include <dt-structs.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2023-03-13 00:30:57 +00:00
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#include <malloc.h>
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#include <regmap.h>
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2015-08-30 22:55:34 +00:00
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#include <syscon.h>
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2019-03-28 03:01:23 +00:00
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#include <asm/arch-rockchip/clock.h>
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2015-08-30 22:55:34 +00:00
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static const struct udevice_id rk3288_syscon_ids[] = {
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{ .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC },
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{ .compatible = "rockchip,rk3288-grf", .data = ROCKCHIP_SYSCON_GRF },
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{ .compatible = "rockchip,rk3288-sgrf", .data = ROCKCHIP_SYSCON_SGRF },
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{ .compatible = "rockchip,rk3288-pmu", .data = ROCKCHIP_SYSCON_PMU },
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{ }
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};
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U_BOOT_DRIVER(syscon_rk3288) = {
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.name = "rk3288_syscon",
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.id = UCLASS_SYSCON,
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.of_match = rk3288_syscon_ids,
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};
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2016-07-04 17:58:33 +00:00
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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2023-03-13 00:30:57 +00:00
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#if IS_ENABLED(CONFIG_FDT_64BIT)
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struct rockchip_rk3288_noc_plat {
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struct dtd_rockchip_rk3288_noc dtplat;
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};
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struct rockchip_rk3288_grf_plat {
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struct dtd_rockchip_rk3288_grf dtplat;
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};
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struct rockchip_rk3288_sgrf_plat {
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struct dtd_rockchip_rk3288_sgrf dtplat;
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};
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struct rockchip_rk3288_pmu_plat {
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struct dtd_rockchip_rk3288_pmu dtplat;
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};
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static int rk3288_noc_bind_of_plat(struct udevice *dev)
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{
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struct rockchip_rk3288_noc_plat *plat = dev_get_plat(dev);
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struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
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int size = dev->uclass->uc_drv->per_device_auto;
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if (size && !priv) {
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priv = calloc(1, size);
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if (!priv)
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return -ENOMEM;
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dev_set_uclass_priv(dev, priv);
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}
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dev->driver_data = dev->driver->of_match->data;
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debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
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return regmap_init_mem_plat(dev, plat->dtplat.reg, sizeof(plat->dtplat.reg[0]),
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ARRAY_SIZE(plat->dtplat.reg) / 2, &priv->regmap);
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}
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static int rk3288_grf_bind_of_plat(struct udevice *dev)
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{
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struct rockchip_rk3288_grf_plat *plat = dev_get_plat(dev);
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struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
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int size = dev->uclass->uc_drv->per_device_auto;
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if (size && !priv) {
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priv = calloc(1, size);
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if (!priv)
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return -ENOMEM;
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dev_set_uclass_priv(dev, priv);
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}
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dev->driver_data = dev->driver->of_match->data;
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debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
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return regmap_init_mem_plat(dev, plat->dtplat.reg, sizeof(plat->dtplat.reg[0]),
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ARRAY_SIZE(plat->dtplat.reg) / 2, &priv->regmap);
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}
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static int rk3288_sgrf_bind_of_plat(struct udevice *dev)
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{
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struct rockchip_rk3288_sgrf_plat *plat = dev_get_plat(dev);
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struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
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int size = dev->uclass->uc_drv->per_device_auto;
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if (size && !priv) {
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priv = calloc(1, size);
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if (!priv)
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return -ENOMEM;
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dev_set_uclass_priv(dev, priv);
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}
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dev->driver_data = dev->driver->of_match->data;
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debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
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return regmap_init_mem_plat(dev, plat->dtplat.reg, sizeof(plat->dtplat.reg[0]),
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ARRAY_SIZE(plat->dtplat.reg) / 2, &priv->regmap);
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}
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static int rk3288_pmu_bind_of_plat(struct udevice *dev)
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{
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struct rockchip_rk3288_pmu_plat *plat = dev_get_plat(dev);
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struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
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int size = dev->uclass->uc_drv->per_device_auto;
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if (size && !priv) {
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priv = calloc(1, size);
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if (!priv)
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return -ENOMEM;
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dev_set_uclass_priv(dev, priv);
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}
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dev->driver_data = dev->driver->of_match->data;
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debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
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return regmap_init_mem_plat(dev, plat->dtplat.reg, sizeof(plat->dtplat.reg[0]),
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ARRAY_SIZE(plat->dtplat.reg) / 2, &priv->regmap);
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}
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#else
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2020-12-03 23:55:23 +00:00
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static int rk3288_syscon_bind_of_plat(struct udevice *dev)
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2016-07-04 17:58:33 +00:00
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{
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dev->driver_data = dev->driver->of_match->data;
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debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
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return 0;
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}
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2023-03-13 00:30:57 +00:00
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#endif
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2016-07-04 17:58:33 +00:00
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U_BOOT_DRIVER(rockchip_rk3288_noc) = {
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.name = "rockchip_rk3288_noc",
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.id = UCLASS_SYSCON,
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.of_match = rk3288_syscon_ids,
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2023-03-13 00:30:57 +00:00
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#if IS_ENABLED(CONFIG_FDT_64BIT)
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.bind = rk3288_noc_bind_of_plat,
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.plat_auto = sizeof(struct rockchip_rk3288_noc_plat),
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#else
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2020-12-03 23:55:23 +00:00
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.bind = rk3288_syscon_bind_of_plat,
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2023-03-13 00:30:57 +00:00
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#endif
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2016-07-04 17:58:33 +00:00
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};
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U_BOOT_DRIVER(rockchip_rk3288_grf) = {
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.name = "rockchip_rk3288_grf",
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.id = UCLASS_SYSCON,
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.of_match = rk3288_syscon_ids + 1,
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2023-03-13 00:30:57 +00:00
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#if IS_ENABLED(CONFIG_FDT_64BIT)
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.bind = rk3288_grf_bind_of_plat,
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.plat_auto = sizeof(struct rockchip_rk3288_grf_plat),
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#else
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2020-12-03 23:55:23 +00:00
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.bind = rk3288_syscon_bind_of_plat,
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2023-03-13 00:30:57 +00:00
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#endif
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2016-07-04 17:58:33 +00:00
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};
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U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
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.name = "rockchip_rk3288_sgrf",
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.id = UCLASS_SYSCON,
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.of_match = rk3288_syscon_ids + 2,
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2023-03-13 00:30:57 +00:00
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#if IS_ENABLED(CONFIG_FDT_64BIT)
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.bind = rk3288_sgrf_bind_of_plat,
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.plat_auto = sizeof(struct rockchip_rk3288_sgrf_plat),
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#else
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2020-12-03 23:55:23 +00:00
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.bind = rk3288_syscon_bind_of_plat,
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2023-03-13 00:30:57 +00:00
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#endif
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2016-07-04 17:58:33 +00:00
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};
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U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
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.name = "rockchip_rk3288_pmu",
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.id = UCLASS_SYSCON,
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.of_match = rk3288_syscon_ids + 3,
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2023-03-13 00:30:57 +00:00
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#if IS_ENABLED(CONFIG_FDT_64BIT)
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.bind = rk3288_pmu_bind_of_plat,
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.plat_auto = sizeof(struct rockchip_rk3288_pmu_plat),
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#else
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2020-12-03 23:55:23 +00:00
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.bind = rk3288_syscon_bind_of_plat,
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2023-03-13 00:30:57 +00:00
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#endif
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2016-07-04 17:58:33 +00:00
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};
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#endif
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