2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2013-03-15 10:07:04 +00:00
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/*
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* hardware_am33xx.h
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*
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* AM33xx hardware specific header
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*
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2023-11-01 20:56:03 +00:00
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* Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
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2013-03-15 10:07:04 +00:00
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*/
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#ifndef __AM33XX_HARDWARE_AM33XX_H
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#define __AM33XX_HARDWARE_AM33XX_H
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2013-03-15 10:07:06 +00:00
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/* Module base addresses */
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/* UART Base Address */
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#define UART0_BASE 0x44E09000
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2017-10-25 13:46:53 +00:00
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#define UART1_BASE 0x48022000
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#define UART2_BASE 0x48024000
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#define UART3_BASE 0x481A6000
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#define UART4_BASE 0x481A8000
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#define UART5_BASE 0x481AA000
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2013-03-15 10:07:06 +00:00
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/* GPIO Base address */
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#define GPIO2_BASE 0x481AC000
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/* Watchdog Timer */
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#define WDT_BASE 0x44E35000
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/* Control Module Base Address */
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#define CTRL_BASE 0x44E10000
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#define CTRL_DEVICE_BASE 0x44E10600
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/* PRCM Base Address */
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#define PRCM_BASE 0x44E00000
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2013-07-30 06:06:28 +00:00
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#define CM_PER 0x44E00000
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#define CM_WKUP 0x44E00400
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2013-12-10 09:32:11 +00:00
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#define CM_DPLL 0x44E00500
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#define CM_RTC 0x44E00800
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2013-07-30 06:06:28 +00:00
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#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
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#define PRM_RSTST (PRM_RSTCTRL + 8)
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2013-03-15 10:07:06 +00:00
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2013-03-15 10:07:04 +00:00
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/* VTP Base address */
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#define VTP0_CTRL_ADDR 0x44E10E0C
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2013-07-02 10:05:59 +00:00
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#define VTP1_CTRL_ADDR 0x48140E10
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2014-12-22 22:26:11 +00:00
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#define PRM_DEVICE_INST 0x44E00F00
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2013-03-15 10:07:04 +00:00
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/* DDR Base address */
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#define DDR_PHY_CMD_ADDR 0x44E12000
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#define DDR_PHY_DATA_ADDR 0x44E120C8
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2013-07-02 10:05:59 +00:00
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#define DDR_PHY_CMD_ADDR2 0x47C0C800
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#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
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2013-03-15 10:07:04 +00:00
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#define DDR_DATA_REGS_NR 2
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2013-07-02 10:05:59 +00:00
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#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
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#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
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2013-03-15 10:07:06 +00:00
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/* CPSW Config space */
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#define CPSW_MDIO_BASE 0x4A101000
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/* RTC base address */
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#define RTC_BASE 0x44E3E000
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2013-07-30 06:06:28 +00:00
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/* OTG */
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#define USB0_OTG_BASE 0x47401000
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#define USB1_OTG_BASE 0x47401800
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2013-08-19 14:38:57 +00:00
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/* LCD Controller */
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#define LCD_CNTL_BASE 0x4830E000
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/* PWMSS */
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#define PWMSS0_BASE 0x48300000
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#define AM33XX_ECAP0_BASE 0x48300100
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2016-09-16 10:21:39 +00:00
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#define AM33XX_EPWM_BASE 0x48300200
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2013-08-19 14:38:57 +00:00
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2013-03-15 10:07:04 +00:00
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#endif /* __AM33XX_HARDWARE_AM33XX_H */
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