2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2017-08-06 23:17:18 +00:00
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/*
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* Board-specific early ddr/sdram init.
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*
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* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
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*/
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.equ PPMCR0, 0xfc04002d
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.equ MSCR_SDRAMC, 0xec094060
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.equ MISCCR2, 0xec09001a
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.equ DDR_RCR, 0xfc0b8180
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.equ DDR_PADCR, 0xfc0b81ac
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.equ DDR_CR00, 0xfc0b8000
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.equ DDR_CR06, 0xfc0b8018
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.equ DDR_CR09, 0xfc0b8024
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.equ DDR_CR40, 0xfc0b80a0
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.equ DDR_CR45, 0xfc0b80b4
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.equ DDR_CR56, 0xfc0b80e0
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.global sbf_dram_init
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.text
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sbf_dram_init:
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/* CD46 = DDR on */
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move.l #PPMCR0, %a1
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move.b #46, (%a1)
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/* stmark 2, max drive strength */
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move.l #MSCR_SDRAMC, %a1
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move.b #1, (%a1)
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/*
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* use cpu clock, seems more realiable
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*
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* DDR2 clock is serviced from DDR controller as input clock / 2
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* so, if clock comes from
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* vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
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* cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
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*
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* .
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* / \ DDR2 can't be clocked lower than 125Mhz
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* / ! \ DDR2 init must pass further i/dcache enable test
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* /_____\
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* WARNING
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*/
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/* cpu / 2 = 125 Mhz for 480 Mhz pll */
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move.l #MISCCR2, %a1
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move.w #0xa01d, (%a1)
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/* DDR force sw reset settings */
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move.l #DDR_RCR, %a1
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move.l #0x00000000, (%a1)
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move.l #0x40000000, (%a1)
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/*
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* PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
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* 500/700 mV are ok
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*/
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move.l #DDR_PADCR, %a1
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move.l #0x01030203, (%a1) /* as freescale tower */
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move.l #DDR_CR00, %a1
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move.l #0x01010101, (%a1)+ /* 0x00 */
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move.l #0x00000101, (%a1)+ /* 0x04 */
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move.l #0x01010100, (%a1)+ /* 0x08 */
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move.l #0x01010000, (%a1)+ /* 0x0C */
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move.l #0x00010101, (%a1)+ /* 0x10 */
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move.l #DDR_CR06, %a1
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move.l #0x00010100, (%a1)+ /* 0x18 */
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move.l #0x00000001, (%a1)+ /* 0x1C */
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move.l #0x01000001, (%a1)+ /* 0x20 */
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move.l #0x00000100, (%a1)+ /* 0x24 */
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move.l #0x00010001, (%a1)+ /* 0x28 */
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move.l #0x00000200, (%a1)+ /* 0x2C */
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move.l #0x01000002, (%a1)+ /* 0x30 */
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move.l #0x00000000, (%a1)+ /* 0x34 */
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move.l #0x00000100, (%a1)+ /* 0x38 */
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move.l #0x02000100, (%a1)+ /* 0x3C */
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move.l #0x02000407, (%a1)+ /* 0x40 */
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move.l #0x02030007, (%a1)+ /* 0x44 */
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move.l #0x02000100, (%a1)+ /* 0x48 */
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move.l #0x0A030203, (%a1)+ /* 0x4C */
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move.l #0x00020708, (%a1)+ /* 0x50 */
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move.l #0x00050008, (%a1)+ /* 0x54 */
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move.l #0x04030002, (%a1)+ /* 0x58 */
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move.l #0x00000004, (%a1)+ /* 0x5C */
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move.l #0x020A0000, (%a1)+ /* 0x60 */
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move.l #0x0C00000E, (%a1)+ /* 0x64 */
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move.l #0x00002004, (%a1)+ /* 0x68 */
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move.l #0x00000000, (%a1)+ /* 0x6C */
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move.l #0x00100010, (%a1)+ /* 0x70 */
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move.l #0x00100010, (%a1)+ /* 0x74 */
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move.l #0x00000000, (%a1)+ /* 0x78 */
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move.l #0x07990000, (%a1)+ /* 0x7C */
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move.l #DDR_CR40, %a1
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move.l #0x00000000, (%a1)+ /* 0xA0 */
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move.l #0x00C80064, (%a1)+ /* 0xA4 */
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move.l #0x44520002, (%a1)+ /* 0xA8 */
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move.l #0x00C80023, (%a1)+ /* 0xAC */
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move.l #DDR_CR45, %a1
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move.l #0x0000C350, (%a1) /* 0xB4 */
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move.l #DDR_CR56, %a1
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move.l #0x04000000, (%a1)+ /* 0xE0 */
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move.l #0x03000304, (%a1)+ /* 0xE4 */
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move.l #0x40040000, (%a1)+ /* 0xE8 */
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move.l #0xC0004004, (%a1)+ /* 0xEC */
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move.l #0x0642C000, (%a1)+ /* 0xF0 */
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move.l #0x00000642, (%a1)+ /* 0xF4 */
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move.l #DDR_CR09, %a1
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tpf
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move.l #0x01000100, (%a1) /* 0x24 */
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move.l #0x2000, %d1
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bsr asm_delay
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rts
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