mirror of
https://github.com/AsahiLinux/u-boot
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303 lines
8.8 KiB
C
303 lines
8.8 KiB
C
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <errno.h>
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#include "cps_drv_lpddr4.h"
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#include "lpddr4_ctl_regs.h"
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#include "lpddr4_if.h"
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#include "lpddr4.h"
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#include "lpddr4_structs_if.h"
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static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound);
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u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
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{
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u32 result = 0U;
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u32 regval = 0U;
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
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regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval);
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CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
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return result;
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}
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u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
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{
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u32 result = 0U;
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u32 lowermask = 0U;
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result = lpddr4_getctlinterruptmasksf(pd, mask);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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lowermask = (u32)(CPS_FLD_READ(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG))));
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*mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG))));
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*mask = (u64)((*mask << WORD_SHIFT) | lowermask);
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}
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return result;
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}
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u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
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{
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u32 result;
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u32 regval = 0;
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const u64 ui64one = 1ULL;
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const u32 ui32irqcount = (u32)LPDDR4_INTR_LOR_BITS + 1U;
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result = lpddr4_setctlinterruptmasksf(pd, mask);
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if ((result == (u32)0) && (ui32irqcount < 64U)) {
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if (*mask >= (ui64one << ui32irqcount))
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result = (u32)EINVAL;
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}
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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regval = (u32)(*mask & WORD_MASK);
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regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG)), regval);
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval);
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regval = (u32)((*mask >> WORD_SHIFT) & WORD_MASK);
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regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG)), regval);
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval);
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}
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return result;
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}
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u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
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{
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u32 result;
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u32 ctlirqstatus = 0;
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u32 fieldshift = 0;
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result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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if ((u32)intr >= (u32)WORD_SHIFT) {
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ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_1__REG));
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fieldshift = (u32)intr - ((u32)WORD_SHIFT);
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} else {
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ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_0__REG));
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fieldshift = (u32)intr;
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}
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if (fieldshift < WORD_SHIFT) {
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if (((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) > 0U)
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*irqstatus = true;
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else
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*irqstatus = false;
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}
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}
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return result;
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}
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u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
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{
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u32 result = 0;
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u32 regval = 0;
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u32 localinterrupt = (u32)intr;
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result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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if (localinterrupt > WORD_SHIFT) {
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localinterrupt = (localinterrupt - (u32)WORD_SHIFT);
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regval = ((u32)LPDDR4_BIT_MASK << localinterrupt);
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), regval);
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} else {
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regval = ((u32)LPDDR4_BIT_MASK << localinterrupt);
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), regval);
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}
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}
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return result;
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}
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void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
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{
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u32 regval;
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u32 errbitmask = 0U;
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u32 snum;
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volatile u32 *regaddress;
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regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
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errbitmask = (LPDDR4_BIT_MASK << 1) | (LPDDR4_BIT_MASK);
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for (snum = 0U; snum < DSLICE_NUM; snum++) {
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regval = CPS_REG_READ(regaddress);
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if ((regval & errbitmask) != 0U) {
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debuginfo->wrlvlerror = CDN_TRUE;
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*errfoundptr = true;
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}
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regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
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}
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}
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static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound)
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{
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volatile u32 *regaddress;
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u32 snum = 0U;
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u32 errbitmask = 0U;
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u32 regval = 0U;
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if (*errorfound == (bool)false) {
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regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG));
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errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK);
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for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
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regval = CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD, CPS_REG_READ(regaddress));
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if ((regval & errbitmask) != RX_CAL_DONE) {
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debuginfo->rxoffseterror = (u8)true;
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*errorfound = true;
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}
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regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
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}
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}
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}
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u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
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{
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u32 result = 0U;
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bool errorfound = false;
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result = lpddr4_getdebuginitinfosf(pd, debuginfo);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
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lpddr4_setsettings(ctlregbase, errorfound);
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lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound);
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errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
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}
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if (errorfound == (bool)true)
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result = (u32)EPROTO;
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return result;
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}
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u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
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{
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u32 result = 0U;
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u32 fldval = 0U;
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result = lpddr4_geteccenablesf(pd, eccparam);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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fldval = CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)));
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switch (fldval) {
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case 3:
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*eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT;
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break;
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case 2:
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*eccparam = LPDDR4_ECC_ERR_DETECT;
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break;
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case 1:
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*eccparam = LPDDR4_ECC_ENABLED;
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break;
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default:
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*eccparam = LPDDR4_ECC_DISABLED;
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break;
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}
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}
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return result;
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}
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u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
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{
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u32 result = 0U;
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u32 regval = 0U;
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result = lpddr4_seteccenablesf(pd, eccparam);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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regval = CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)), *eccparam);
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval);
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}
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return result;
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}
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u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
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{
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u32 result = 0U;
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result = lpddr4_getreducmodesf(pd, mode);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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if (CPS_FLD_READ(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U)
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*mode = LPDDR4_REDUC_ON;
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else
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*mode = LPDDR4_REDUC_OFF;
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}
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return result;
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}
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u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
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{
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u32 result = 0U;
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u32 regval = 0U;
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result = lpddr4_setreducmodesf(pd, mode);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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regval = (u32)CPS_FLD_WRITE(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG)), *mode);
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval);
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}
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return result;
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}
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u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
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{
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u32 lowerdata;
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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u32 result = (u32)0;
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if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
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*mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
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*mmrvalue = (u64)0;
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result = (u32)EIO;
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} else {
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*mrrstatus = (u8)0;
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lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
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*mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
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*mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
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result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
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}
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return result;
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}
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#ifdef REG_WRITE_VERIF
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u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
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{
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u32 rwmask = 0U;
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switch (dslicenum) {
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case 0:
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if (arrayoffset < DSLICE0_REG_COUNT)
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rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
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break;
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case 1:
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if (arrayoffset < DSLICE1_REG_COUNT)
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rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
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break;
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case 2:
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if (arrayoffset < DSLICE2_REG_COUNT)
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rwmask = g_lpddr4_data_slice_2_rw_mask[arrayoffset];
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break;
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default:
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if (arrayoffset < DSLICE3_REG_COUNT)
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rwmask = g_lpddr4_data_slice_3_rw_mask[arrayoffset];
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break;
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}
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return rwmask;
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}
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#endif
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