2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2011-10-03 08:19:53 +00:00
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/*
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2022-01-30 23:02:30 +00:00
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* Copyright (C) 2021-2022 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2011 Jason Cooper <u-boot@lakedaemon.net>
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2011-10-03 08:19:53 +00:00
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*
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* Based on work by:
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Siddarth Gore <gores@marvell.com>
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*/
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#include <common.h>
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2020-05-10 17:40:02 +00:00
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#include <init.h>
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2022-01-30 23:02:30 +00:00
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#include <netdev.h>
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2011-10-29 11:19:47 +00:00
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#include <asm/arch/cpu.h>
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2014-10-22 10:13:06 +00:00
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#include <asm/arch/soc.h>
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2011-10-03 08:19:53 +00:00
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#include <asm/arch/mpp.h>
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2020-10-31 03:38:53 +00:00
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#include <asm/global_data.h>
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2011-10-03 08:19:53 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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2022-01-30 23:02:30 +00:00
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#define DREAMPLUG_OE_LOW (~(0))
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#define DREAMPLUG_OE_HIGH (~(0))
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#define DREAMPLUG_OE_VAL_LOW 0
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#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
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2011-10-03 08:19:53 +00:00
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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2014-10-22 10:13:11 +00:00
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mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
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DREAMPLUG_OE_VAL_HIGH,
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DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
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2011-10-03 08:19:53 +00:00
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/* Multi-Purpose Pins Functionality configuration */
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2012-11-26 11:27:36 +00:00
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static const u32 kwmpp_config[] = {
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2011-10-03 08:19:53 +00:00
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MPP0_SPI_SCn, /* SPI Flash */
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MPP1_SPI_MOSI,
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MPP2_SPI_SCK,
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MPP3_SPI_MISO,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD, /* Serial */
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MPP11_UART0_RXD,
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MPP12_SD_CLK, /* SDIO Slot */
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MPP13_SD_CMD,
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MPP14_SD_D0,
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MPP15_SD_D1,
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MPP16_SD_D2,
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MPP17_SD_D3,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GE1_0, /* Gigabit Ethernet */
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MPP21_GE1_1,
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MPP22_GE1_2,
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MPP23_GE1_3,
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MPP24_GE1_4,
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MPP25_GE1_5,
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MPP26_GE1_6,
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MPP27_GE1_7,
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MPP28_GE1_8,
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MPP29_GE1_9,
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MPP30_GE1_10,
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MPP31_GE1_11,
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MPP32_GE1_12,
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MPP33_GE1_13,
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MPP34_GE1_14,
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MPP35_GE1_15,
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MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_TDM_SPI_SCK,
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MPP41_TDM_SPI_MISO,
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MPP42_TDM_SPI_MOSI,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO,
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MPP47_GPIO, /* Bluetooth LED */
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MPP48_GPIO, /* Wifi LED */
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MPP49_GPIO, /* Wifi AP LED */
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0
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};
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2012-06-01 01:31:00 +00:00
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kirkwood_mpp_conf(kwmpp_config, NULL);
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2011-10-03 08:19:53 +00:00
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return 0;
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}
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2022-01-30 23:02:30 +00:00
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int board_eth_init(struct bd_info *bis)
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2011-10-03 08:19:53 +00:00
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{
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2022-01-30 23:02:30 +00:00
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return cpu_eth_init(bis);
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2011-10-03 08:19:53 +00:00
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}
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2022-01-30 23:02:30 +00:00
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int board_init(void)
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2011-10-03 08:19:53 +00:00
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{
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2022-01-30 23:02:30 +00:00
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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2021-07-26 06:01:19 +00:00
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2022-01-30 23:02:30 +00:00
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return 0;
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2011-10-03 08:19:53 +00:00
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}
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