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u-boot/drivers/pinctrl/intel/Kconfig

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x86: Add a generic Intel pinctrl driver Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:53 +00:00
#
# Intel PINCTRL drivers
#
if PINCTRL_INTEL
config INTEL_PINCTRL_DUAL_ROUTE_SUPPORT
x86: apl: Add pinctrl driver Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:32:08 +00:00
bool
default y
x86: Add a generic Intel pinctrl driver Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:53 +00:00
config INTEL_PINCTRL_PADCFG_PADTOL
x86: apl: Add pinctrl driver Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:32:08 +00:00
bool n
x86: Add a generic Intel pinctrl driver Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:53 +00:00
config INTEL_PINCTRL_IOSTANDBY
x86: apl: Add pinctrl driver Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:32:08 +00:00
bool
default y
x86: pinctrl: Add multi-ACPI control Add a Kconfig to control whether pinctrl is represented as a single ACPI device or as multiple devices. In the latter case (the default) we should return the pin number relative to the pinctrl device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-08 03:32:21 +00:00
config INTEL_PINCTRL_MULTI_ACPI_DEVICES
bool
default y
help
Enable this if the pinctrl devices are modelled as multiple,
separate ACPI devices in the ACPI tables. If enabled, the ACPI
devices match the U-Boot pinctrl devices and the pin 'offset' is
relatove to a particular pinctrl device. If disabled, there is a
single ACPI pinctrl device which includes all U-Boot pinctrl devices
and the pin 'offset' is in effect a global pin number.
x86: apl: Add pinctrl driver Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:32:08 +00:00
config PINCTRL_INTEL_APL
bool "Support Intel Apollo Lake (APL)"
help
Add support for Intel Apollo Lake pin-control and pin-mux settings.
These are mostly read from the device tree, with the early-pads
property in the host bridge and the pads property in the fsp-s
subnode of the host bridge.
x86: Add a generic Intel pinctrl driver Recent Intel SoCs share a pinctrl mechanism with many common elements. Add an implementation of this core functionality, allowing SoC-specific drivers to avoid adding common code. As well as a pinctrl driver this provides a GPIO driver based on the same code. Once other SoCs use this driver we may consider moving more properties to the device tree (e.g. the community info and pad definitions). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:53 +00:00
endif
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