2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2014-12-15 05:24:28 +00:00
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/*
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* Bus Matrix header file for the SAMA5 family
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*
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* Copyright (C) 2014 Atmel
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* Bo Shen <voice.shen@atmel.com>
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*/
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#ifndef __SAMA5_MATRIX_H
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#define __SAMA5_MATRIX_H
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struct atmel_matrix {
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u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
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u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
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u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
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u32 res1[20]; /* 0x100 ~ 0x14c */
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u32 meier; /* 0x150: Master Error Interrupt Enable Register */
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u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
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u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
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u32 mesr; /* 0x15c: Master Error Status Register */
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u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
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u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
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u32 wpmr; /* 0x1E4: Write Protection Mode Register */
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u32 wpsr; /* 0x1E8: Write Protection Status Register */
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u32 res3[5]; /* 0x1EC ~ 0x1FC */
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u32 ssr[16]; /* 0x200 ~ 0x23c: Security Slave Register */
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u32 sassr[16]; /* 0x240 ~ 0x27c: Security Areas Split Slave Register */
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u32 srtsr[16]; /* 0x280 ~ 0x2bc: Security Region Top Slave */
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u32 spselr[3]; /* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */
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};
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/* Bit field in WPMR */
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#define ATMEL_MATRIX_WPMR_WPKEY 0x4D415400
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#define ATMEL_MATRIX_WPMR_WPEN 0x00000001
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#endif
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