2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2013-12-14 03:47:35 +00:00
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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2016-03-04 00:09:47 +00:00
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* (C) Copyright 2016
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* Alexander Graf <agraf@suse.de>
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2013-12-14 03:47:35 +00:00
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*/
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#include <common.h>
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2019-11-14 19:57:37 +00:00
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#include <cpu_func.h>
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2019-12-28 17:45:07 +00:00
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#include <hang.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2020-05-10 17:39:56 +00:00
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#include <asm/cache.h>
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2020-10-31 03:38:53 +00:00
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#include <asm/global_data.h>
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2013-12-14 03:47:35 +00:00
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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2019-05-03 13:41:00 +00:00
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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2015-10-14 16:55:45 +00:00
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2016-03-04 00:09:47 +00:00
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/*
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* With 4k page granule, a virtual address is split into 4 lookup parts
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* spanning 9 bits each:
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*
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* _______________________________________________
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* | | | | | | |
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* | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
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* |_______|_______|_______|_______|_______|_______|
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* 63-48 47-39 38-30 29-21 20-12 11-00
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*
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* mask page size
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*
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* Lv0: FF8000000000 --
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* Lv1: 7FC0000000 1G
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* Lv2: 3FE00000 2M
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* Lv3: 1FF000 4K
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* off: FFF
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*/
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2015-10-14 16:55:45 +00:00
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2016-06-24 23:46:20 +00:00
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u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
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2016-03-04 00:09:45 +00:00
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{
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u64 max_addr = 0;
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u64 ips, va_bits;
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u64 tcr;
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int i;
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/* Find the largest address we need to support */
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2016-03-04 00:09:48 +00:00
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for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
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2016-06-24 23:46:22 +00:00
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max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
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2016-03-04 00:09:45 +00:00
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/* Calculate the maximum physical (and thus virtual) address */
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if (max_addr > (1ULL << 44)) {
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ips = 5;
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va_bits = 48;
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} else if (max_addr > (1ULL << 42)) {
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ips = 4;
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va_bits = 44;
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} else if (max_addr > (1ULL << 40)) {
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ips = 3;
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va_bits = 42;
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} else if (max_addr > (1ULL << 36)) {
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ips = 2;
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va_bits = 40;
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} else if (max_addr > (1ULL << 32)) {
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ips = 1;
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va_bits = 36;
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} else {
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ips = 0;
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va_bits = 32;
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}
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if (el == 1) {
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2016-03-04 00:09:46 +00:00
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tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
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2016-03-04 00:09:45 +00:00
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} else if (el == 2) {
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tcr = TCR_EL2_RSVD | (ips << 16);
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} else {
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tcr = TCR_EL3_RSVD | (ips << 16);
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}
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/* PTWs cacheable, inner/outer WBWA and inner shareable */
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2016-03-04 00:09:47 +00:00
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tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
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tcr |= TCR_T0SZ(va_bits);
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2016-03-04 00:09:45 +00:00
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if (pips)
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*pips = ips;
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if (pva_bits)
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*pva_bits = va_bits;
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return tcr;
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}
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2016-03-04 00:09:47 +00:00
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#define MAX_PTE_ENTRIES 512
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static int pte_type(u64 *pte)
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{
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return *pte & PTE_TYPE_MASK;
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}
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/* Returns the LSB number for a PTE on level <level> */
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static int level2shift(int level)
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{
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/* Page is 12 bits wide, every level translates 9 bits */
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return (12 + 9 * (3 - level));
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}
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static u64 *find_pte(u64 addr, int level)
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2015-10-14 16:55:45 +00:00
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{
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2016-03-04 00:09:47 +00:00
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int start_level = 0;
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u64 *pte;
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u64 idx;
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u64 va_bits;
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int i;
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debug("addr=%llx level=%d\n", addr, level);
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get_tcr(0, NULL, &va_bits);
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if (va_bits < 39)
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start_level = 1;
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if (level < start_level)
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return NULL;
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/* Walk through all page table levels to find our PTE */
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pte = (u64*)gd->arch.tlb_addr;
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for (i = start_level; i < 4; i++) {
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idx = (addr >> level2shift(i)) & 0x1FF;
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pte += idx;
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debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
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/* Found it */
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if (i == level)
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return pte;
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/* PTE is no table (either invalid or block), can't traverse */
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if (pte_type(pte) != PTE_TYPE_TABLE)
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return NULL;
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/* Off to the next level */
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pte = (u64*)(*pte & 0x0000fffffffff000ULL);
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}
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/* Should never reach here */
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return NULL;
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}
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/* Returns and creates a new full table (512 entries) */
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static u64 *create_table(void)
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{
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u64 *new_table = (u64*)gd->arch.tlb_fillptr;
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u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
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/* Allocate MAX_PTE_ENTRIES pte entries */
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gd->arch.tlb_fillptr += pt_len;
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if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
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panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
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"Please increase the size in get_page_table_size()",
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gd->arch.tlb_fillptr - gd->arch.tlb_addr,
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gd->arch.tlb_size);
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/* Mark all entries as invalid */
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memset(new_table, 0, pt_len);
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return new_table;
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}
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static void set_pte_table(u64 *pte, u64 *table)
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{
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/* Point *pte to the new table */
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debug("Setting %p to addr=%p\n", pte, table);
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*pte = PTE_TYPE_TABLE | (ulong)table;
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}
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2016-06-24 23:46:21 +00:00
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/* Splits a block PTE into table with subpages spanning the old block */
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static void split_block(u64 *pte, int level)
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{
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u64 old_pte = *pte;
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u64 *new_table;
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u64 i = 0;
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/* level describes the parent level, we need the child ones */
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int levelshift = level2shift(level + 1);
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if (pte_type(pte) != PTE_TYPE_BLOCK)
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panic("PTE %p (%llx) is not a block. Some driver code wants to "
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"modify dcache settings for an range not covered in "
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"mem_map.", pte, old_pte);
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new_table = create_table();
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debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
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for (i = 0; i < MAX_PTE_ENTRIES; i++) {
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new_table[i] = old_pte | (i << levelshift);
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/* Level 3 block PTEs have the table type */
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if ((level + 1) == 3)
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new_table[i] |= PTE_TYPE_TABLE;
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debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
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}
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/* Set the new table into effect */
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set_pte_table(pte, new_table);
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}
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2016-03-04 00:09:47 +00:00
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/* Add one mm_region map entry to the page tables */
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static void add_map(struct mm_region *map)
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{
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u64 *pte;
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2016-06-24 23:46:22 +00:00
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u64 virt = map->virt;
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u64 phys = map->phys;
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2016-03-04 00:09:47 +00:00
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u64 size = map->size;
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u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
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u64 blocksize;
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int level;
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u64 *new_table;
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while (size) {
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2016-06-24 23:46:22 +00:00
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pte = find_pte(virt, 0);
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2016-03-04 00:09:47 +00:00
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if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
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2016-06-24 23:46:22 +00:00
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debug("Creating table for virt 0x%llx\n", virt);
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2016-03-04 00:09:47 +00:00
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new_table = create_table();
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set_pte_table(pte, new_table);
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}
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for (level = 1; level < 4; level++) {
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2016-06-24 23:46:22 +00:00
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pte = find_pte(virt, level);
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2016-06-24 23:46:21 +00:00
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if (!pte)
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panic("pte not found\n");
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2016-06-24 23:46:22 +00:00
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2016-03-04 00:09:47 +00:00
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blocksize = 1ULL << level2shift(level);
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2016-06-24 23:46:22 +00:00
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debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
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virt, size, blocksize);
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if (size >= blocksize && !(virt & (blocksize - 1))) {
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2016-03-04 00:09:47 +00:00
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/* Page fits, create block PTE */
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2016-06-24 23:46:22 +00:00
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debug("Setting PTE %p to block virt=%llx\n",
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pte, virt);
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2017-11-28 02:31:28 +00:00
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if (level == 3)
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*pte = phys | attrs | PTE_TYPE_PAGE;
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else
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*pte = phys | attrs;
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2016-06-24 23:46:22 +00:00
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virt += blocksize;
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phys += blocksize;
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2016-03-04 00:09:47 +00:00
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size -= blocksize;
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break;
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2016-06-24 23:46:21 +00:00
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} else if (pte_type(pte) == PTE_TYPE_FAULT) {
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2016-03-04 00:09:47 +00:00
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/* Page doesn't fit, create subpages */
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2016-06-24 23:46:22 +00:00
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debug("Creating subtable for virt 0x%llx blksize=%llx\n",
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virt, blocksize);
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2016-03-04 00:09:47 +00:00
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new_table = create_table();
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set_pte_table(pte, new_table);
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2016-06-24 23:46:21 +00:00
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} else if (pte_type(pte) == PTE_TYPE_BLOCK) {
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2016-06-24 23:46:22 +00:00
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debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
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virt, blocksize);
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2016-06-24 23:46:21 +00:00
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split_block(pte, level);
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2016-03-04 00:09:47 +00:00
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}
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}
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}
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}
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enum pte_type {
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PTE_INVAL,
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PTE_BLOCK,
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PTE_LEVEL,
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};
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/*
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* This is a recursively called function to count the number of
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* page tables we need to cover a particular PTE range. If you
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* call this with level = -1 you basically get the full 48 bit
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* coverage.
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*/
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static int count_required_pts(u64 addr, int level, u64 maxaddr)
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{
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int levelshift = level2shift(level);
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u64 levelsize = 1ULL << levelshift;
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u64 levelmask = levelsize - 1;
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u64 levelend = addr + levelsize;
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int r = 0;
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int i;
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enum pte_type pte_type = PTE_INVAL;
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2016-03-04 00:09:48 +00:00
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for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
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2016-03-04 00:09:47 +00:00
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struct mm_region *map = &mem_map[i];
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2016-06-24 23:46:22 +00:00
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u64 start = map->virt;
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2016-03-04 00:09:47 +00:00
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u64 end = start + map->size;
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/* Check if the PTE would overlap with the map */
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if (max(addr, start) <= min(levelend, end)) {
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start = max(addr, start);
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end = min(levelend, end);
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/* We need a sub-pt for this level */
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if ((start & levelmask) || (end & levelmask)) {
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pte_type = PTE_LEVEL;
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break;
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2015-10-14 16:55:45 +00:00
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}
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2016-03-04 00:09:47 +00:00
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/* Lv0 can not do block PTEs, so do levels here too */
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if (level <= 0) {
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pte_type = PTE_LEVEL;
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break;
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}
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/* PTE is active, but fits into a block */
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pte_type = PTE_BLOCK;
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2015-10-14 16:55:45 +00:00
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}
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}
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2016-03-04 00:09:47 +00:00
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/*
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* Block PTEs at this level are already covered by the parent page
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* table, so we only need to count sub page tables.
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*/
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if (pte_type == PTE_LEVEL) {
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int sublevel = level + 1;
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u64 sublevelsize = 1ULL << level2shift(sublevel);
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/* Account for the new sub page table ... */
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r = 1;
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/* ... and for all child page tables that one might have */
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for (i = 0; i < MAX_PTE_ENTRIES; i++) {
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r += count_required_pts(addr, sublevel, maxaddr);
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addr += sublevelsize;
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if (addr >= maxaddr) {
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/*
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* We reached the end of address space, no need
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* to look any further.
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*/
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break;
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}
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}
|
|
|
|
}
|
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Returns the estimated required size of all page tables */
|
2016-03-21 19:26:12 +00:00
|
|
|
__weak u64 get_page_table_size(void)
|
2016-03-04 00:09:47 +00:00
|
|
|
{
|
|
|
|
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
|
|
|
|
u64 size = 0;
|
|
|
|
u64 va_bits;
|
|
|
|
int start_level = 0;
|
|
|
|
|
|
|
|
get_tcr(0, NULL, &va_bits);
|
|
|
|
if (va_bits < 39)
|
|
|
|
start_level = 1;
|
|
|
|
|
|
|
|
/* Account for all page tables we would need to cover our memory map */
|
|
|
|
size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We need to duplicate our page table once to have an emergency pt to
|
|
|
|
* resort to when splitting page tables later on
|
|
|
|
*/
|
|
|
|
size *= 2;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We may need to split page tables later on if dcache settings change,
|
|
|
|
* so reserve up to 4 (random pick) page tables for that.
|
|
|
|
*/
|
|
|
|
size += one_pt * 4;
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
2016-06-24 23:46:20 +00:00
|
|
|
void setup_pgtables(void)
|
2016-03-04 00:09:47 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2016-06-24 23:46:20 +00:00
|
|
|
if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
|
|
|
|
panic("Page table pointer not setup.");
|
|
|
|
|
2016-03-04 00:09:47 +00:00
|
|
|
/*
|
|
|
|
* Allocate the first level we're on with invalidate entries.
|
|
|
|
* If the starting level is 0 (va_bits >= 39), then this is our
|
|
|
|
* Lv0 page table, otherwise it's the entry Lv1 page table.
|
|
|
|
*/
|
|
|
|
create_table();
|
|
|
|
|
|
|
|
/* Now add all MMU table entries one after another to the table */
|
2016-03-04 00:09:48 +00:00
|
|
|
for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
|
2016-03-04 00:09:47 +00:00
|
|
|
add_map(&mem_map[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void setup_all_pgtables(void)
|
|
|
|
{
|
|
|
|
u64 tlb_addr = gd->arch.tlb_addr;
|
2016-07-30 21:13:03 +00:00
|
|
|
u64 tlb_size = gd->arch.tlb_size;
|
2016-03-04 00:09:47 +00:00
|
|
|
|
|
|
|
/* Reset the fill ptr */
|
|
|
|
gd->arch.tlb_fillptr = tlb_addr;
|
|
|
|
|
|
|
|
/* Create normal system page tables */
|
|
|
|
setup_pgtables();
|
|
|
|
|
|
|
|
/* Create emergency page tables */
|
2016-07-30 21:13:03 +00:00
|
|
|
gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
|
|
|
|
(uintptr_t)gd->arch.tlb_addr;
|
2016-03-04 00:09:47 +00:00
|
|
|
gd->arch.tlb_addr = gd->arch.tlb_fillptr;
|
|
|
|
setup_pgtables();
|
|
|
|
gd->arch.tlb_emerg = gd->arch.tlb_addr;
|
|
|
|
gd->arch.tlb_addr = tlb_addr;
|
2016-07-30 21:13:03 +00:00
|
|
|
gd->arch.tlb_size = tlb_size;
|
2015-10-14 16:55:45 +00:00
|
|
|
}
|
|
|
|
|
2013-12-14 03:47:35 +00:00
|
|
|
/* to activate the MMU we need to set up virtual memory */
|
2015-10-05 18:09:00 +00:00
|
|
|
__weak void mmu_setup(void)
|
2013-12-14 03:47:35 +00:00
|
|
|
{
|
2015-07-22 23:10:11 +00:00
|
|
|
int el;
|
2013-12-14 03:47:35 +00:00
|
|
|
|
2016-03-04 00:09:47 +00:00
|
|
|
/* Set up page tables only once */
|
|
|
|
if (!gd->arch.tlb_fillptr)
|
|
|
|
setup_all_pgtables();
|
2016-03-04 00:09:45 +00:00
|
|
|
|
|
|
|
el = current_el();
|
|
|
|
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
|
|
|
|
MEMORY_ATTRIBUTES);
|
|
|
|
|
2013-12-14 03:47:35 +00:00
|
|
|
/* enable the mmu */
|
|
|
|
set_sctlr(get_sctlr() | CR_M);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Performs a invalidation of the entire data cache at all levels
|
|
|
|
*/
|
|
|
|
void invalidate_dcache_all(void)
|
|
|
|
{
|
2014-02-26 21:26:04 +00:00
|
|
|
__asm_invalidate_dcache_all();
|
2016-10-19 21:18:46 +00:00
|
|
|
__asm_invalidate_l3_dcache();
|
2013-12-14 03:47:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2015-01-06 21:18:42 +00:00
|
|
|
* Performs a clean & invalidation of the entire data cache at all levels.
|
|
|
|
* This function needs to be inline to avoid using stack.
|
2016-10-19 21:18:46 +00:00
|
|
|
* __asm_flush_l3_dcache return status of timeout
|
2013-12-14 03:47:35 +00:00
|
|
|
*/
|
2015-01-06 21:18:42 +00:00
|
|
|
inline void flush_dcache_all(void)
|
2013-12-14 03:47:35 +00:00
|
|
|
{
|
2015-01-06 21:18:42 +00:00
|
|
|
int ret;
|
|
|
|
|
2013-12-14 03:47:35 +00:00
|
|
|
__asm_flush_dcache_all();
|
2016-10-19 21:18:46 +00:00
|
|
|
ret = __asm_flush_l3_dcache();
|
2015-01-06 21:18:42 +00:00
|
|
|
if (ret)
|
|
|
|
debug("flushing dcache returns 0x%x\n", ret);
|
|
|
|
else
|
|
|
|
debug("flushing dcache successfully.\n");
|
2013-12-14 03:47:35 +00:00
|
|
|
}
|
|
|
|
|
2019-04-22 16:13:32 +00:00
|
|
|
#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
|
2013-12-14 03:47:35 +00:00
|
|
|
/*
|
|
|
|
* Invalidates range in all levels of D-cache/unified cache
|
|
|
|
*/
|
|
|
|
void invalidate_dcache_range(unsigned long start, unsigned long stop)
|
|
|
|
{
|
2017-04-05 23:53:18 +00:00
|
|
|
__asm_invalidate_dcache_range(start, stop);
|
2013-12-14 03:47:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flush range(clean & invalidate) from all levels of D-cache/unified cache
|
|
|
|
*/
|
|
|
|
void flush_dcache_range(unsigned long start, unsigned long stop)
|
|
|
|
{
|
|
|
|
__asm_flush_dcache_range(start, stop);
|
|
|
|
}
|
2019-04-22 16:13:32 +00:00
|
|
|
#else
|
|
|
|
void invalidate_dcache_range(unsigned long start, unsigned long stop)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void flush_dcache_range(unsigned long start, unsigned long stop)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
|
2013-12-14 03:47:35 +00:00
|
|
|
|
|
|
|
void dcache_enable(void)
|
|
|
|
{
|
|
|
|
/* The data cache is not active unless the mmu is enabled */
|
|
|
|
if (!(get_sctlr() & CR_M)) {
|
|
|
|
invalidate_dcache_all();
|
|
|
|
__asm_invalidate_tlb_all();
|
|
|
|
mmu_setup();
|
|
|
|
}
|
|
|
|
|
|
|
|
set_sctlr(get_sctlr() | CR_C);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dcache_disable(void)
|
|
|
|
{
|
|
|
|
uint32_t sctlr;
|
|
|
|
|
|
|
|
sctlr = get_sctlr();
|
|
|
|
|
|
|
|
/* if cache isn't enabled no need to disable */
|
|
|
|
if (!(sctlr & CR_C))
|
|
|
|
return;
|
|
|
|
|
|
|
|
set_sctlr(sctlr & ~(CR_C|CR_M));
|
|
|
|
|
|
|
|
flush_dcache_all();
|
|
|
|
__asm_invalidate_tlb_all();
|
|
|
|
}
|
|
|
|
|
|
|
|
int dcache_status(void)
|
|
|
|
{
|
|
|
|
return (get_sctlr() & CR_C) != 0;
|
|
|
|
}
|
|
|
|
|
2015-06-26 12:35:07 +00:00
|
|
|
u64 *__weak arch_get_page_table(void) {
|
|
|
|
puts("No page table offset defined\n");
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-03-04 00:09:47 +00:00
|
|
|
static bool is_aligned(u64 addr, u64 size, u64 align)
|
|
|
|
{
|
|
|
|
return !(addr & (align - 1)) && !(size & (align - 1));
|
|
|
|
}
|
|
|
|
|
2017-03-06 17:02:33 +00:00
|
|
|
/* Use flag to indicate if attrs has more than d-cache attributes */
|
|
|
|
static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
|
2016-03-04 00:09:47 +00:00
|
|
|
{
|
|
|
|
int levelshift = level2shift(level);
|
|
|
|
u64 levelsize = 1ULL << levelshift;
|
|
|
|
u64 *pte = find_pte(start, level);
|
|
|
|
|
|
|
|
/* Can we can just modify the current level block PTE? */
|
|
|
|
if (is_aligned(start, size, levelsize)) {
|
2017-03-06 17:02:33 +00:00
|
|
|
if (flag) {
|
|
|
|
*pte &= ~PMD_ATTRMASK;
|
|
|
|
*pte |= attrs & PMD_ATTRMASK;
|
|
|
|
} else {
|
|
|
|
*pte &= ~PMD_ATTRINDX_MASK;
|
|
|
|
*pte |= attrs & PMD_ATTRINDX_MASK;
|
|
|
|
}
|
2016-03-04 00:09:47 +00:00
|
|
|
debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
|
|
|
|
|
|
|
|
return levelsize;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Unaligned or doesn't fit, maybe split block into table */
|
|
|
|
debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
|
|
|
|
|
|
|
|
/* Maybe we need to split the block into a table */
|
|
|
|
if (pte_type(pte) == PTE_TYPE_BLOCK)
|
|
|
|
split_block(pte, level);
|
|
|
|
|
|
|
|
/* And then double-check it became a table or already is one */
|
|
|
|
if (pte_type(pte) != PTE_TYPE_TABLE)
|
|
|
|
panic("PTE %p (%llx) for addr=%llx should be a table",
|
|
|
|
pte, *pte, start);
|
|
|
|
|
|
|
|
/* Roll on to the next page table level */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
|
|
|
|
enum dcache_option option)
|
|
|
|
{
|
2020-05-11 08:41:07 +00:00
|
|
|
u64 attrs = PMD_ATTRINDX(option >> 2);
|
2016-03-04 00:09:47 +00:00
|
|
|
u64 real_start = start;
|
|
|
|
u64 real_size = size;
|
|
|
|
|
|
|
|
debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
|
|
|
|
|
2016-06-24 23:46:20 +00:00
|
|
|
if (!gd->arch.tlb_emerg)
|
|
|
|
panic("Emergency page table not setup.");
|
|
|
|
|
2016-03-04 00:09:47 +00:00
|
|
|
/*
|
|
|
|
* We can not modify page tables that we're currently running on,
|
|
|
|
* so we first need to switch to the "emergency" page tables where
|
|
|
|
* we can safely modify our primary page tables and then switch back
|
|
|
|
*/
|
|
|
|
__asm_switch_ttbr(gd->arch.tlb_emerg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Loop through the address range until we find a page granule that fits
|
|
|
|
* our alignment constraints, then set it to the new cache attributes
|
|
|
|
*/
|
|
|
|
while (size > 0) {
|
|
|
|
int level;
|
|
|
|
u64 r;
|
|
|
|
|
|
|
|
for (level = 1; level < 4; level++) {
|
2017-03-06 17:02:33 +00:00
|
|
|
/* Set d-cache attributes only */
|
|
|
|
r = set_one_region(start, size, attrs, false, level);
|
2016-03-04 00:09:47 +00:00
|
|
|
if (r) {
|
|
|
|
/* PTE successfully replaced */
|
|
|
|
size -= r;
|
|
|
|
start += r;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We're done modifying page tables, switch back to our primary ones */
|
|
|
|
__asm_switch_ttbr(gd->arch.tlb_addr);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure there's nothing stale in dcache for a region that might
|
|
|
|
* have caches off now
|
|
|
|
*/
|
|
|
|
flush_dcache_range(real_start, real_start + real_size);
|
|
|
|
}
|
2015-10-14 16:55:45 +00:00
|
|
|
|
2017-03-06 17:02:33 +00:00
|
|
|
/*
|
|
|
|
* Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
|
|
|
|
* The procecess is break-before-make. The target region will be marked as
|
|
|
|
* invalid during the process of changing.
|
|
|
|
*/
|
|
|
|
void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
|
|
|
|
{
|
|
|
|
int level;
|
|
|
|
u64 r, size, start;
|
|
|
|
|
|
|
|
start = addr;
|
|
|
|
size = siz;
|
|
|
|
/*
|
|
|
|
* Loop through the address range until we find a page granule that fits
|
|
|
|
* our alignment constraints, then set it to "invalid".
|
|
|
|
*/
|
|
|
|
while (size > 0) {
|
|
|
|
for (level = 1; level < 4; level++) {
|
|
|
|
/* Set PTE to fault */
|
|
|
|
r = set_one_region(start, size, PTE_TYPE_FAULT, true,
|
|
|
|
level);
|
|
|
|
if (r) {
|
|
|
|
/* PTE successfully invalidated */
|
|
|
|
size -= r;
|
|
|
|
start += r;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
flush_dcache_range(gd->arch.tlb_addr,
|
|
|
|
gd->arch.tlb_addr + gd->arch.tlb_size);
|
|
|
|
__asm_invalidate_tlb_all();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Loop through the address range until we find a page granule that fits
|
|
|
|
* our alignment constraints, then set it to the new cache attributes
|
|
|
|
*/
|
|
|
|
start = addr;
|
|
|
|
size = siz;
|
|
|
|
while (size > 0) {
|
|
|
|
for (level = 1; level < 4; level++) {
|
|
|
|
/* Set PTE to new attributes */
|
|
|
|
r = set_one_region(start, size, attrs, true, level);
|
|
|
|
if (r) {
|
|
|
|
/* PTE successfully updated */
|
|
|
|
size -= r;
|
|
|
|
start += r;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
flush_dcache_range(gd->arch.tlb_addr,
|
|
|
|
gd->arch.tlb_addr + gd->arch.tlb_size);
|
|
|
|
__asm_invalidate_tlb_all();
|
|
|
|
}
|
|
|
|
|
2019-05-03 13:41:00 +00:00
|
|
|
#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
|
2013-12-14 03:47:35 +00:00
|
|
|
|
2016-03-04 00:09:55 +00:00
|
|
|
/*
|
|
|
|
* For SPL builds, we may want to not have dcache enabled. Any real U-Boot
|
|
|
|
* running however really wants to have dcache and the MMU active. Check that
|
|
|
|
* everything is sane and give the developer a hint if it isn't.
|
|
|
|
*/
|
|
|
|
#ifndef CONFIG_SPL_BUILD
|
|
|
|
#error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
|
|
|
|
#endif
|
|
|
|
|
2013-12-14 03:47:35 +00:00
|
|
|
void invalidate_dcache_all(void)
|
|
|
|
{
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}
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|
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void flush_dcache_all(void)
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|
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{
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|
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}
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void dcache_enable(void)
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|
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|
{
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|
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}
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void dcache_disable(void)
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|
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{
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|
}
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int dcache_status(void)
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|
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|
{
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|
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|
return 0;
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|
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}
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|
|
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|
2015-06-26 12:35:07 +00:00
|
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|
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
|
|
|
|
enum dcache_option option)
|
|
|
|
{
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|
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}
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|
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|
2019-05-03 13:41:00 +00:00
|
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|
#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
|
2013-12-14 03:47:35 +00:00
|
|
|
|
2019-05-03 13:41:00 +00:00
|
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|
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
|
2013-12-14 03:47:35 +00:00
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|
|
void icache_enable(void)
|
|
|
|
{
|
2016-10-19 21:18:46 +00:00
|
|
|
invalidate_icache_all();
|
2013-12-14 03:47:35 +00:00
|
|
|
set_sctlr(get_sctlr() | CR_I);
|
|
|
|
}
|
|
|
|
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|
|
|
void icache_disable(void)
|
|
|
|
{
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|
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|
set_sctlr(get_sctlr() & ~CR_I);
|
|
|
|
}
|
|
|
|
|
|
|
|
int icache_status(void)
|
|
|
|
{
|
|
|
|
return (get_sctlr() & CR_I) != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void invalidate_icache_all(void)
|
|
|
|
{
|
|
|
|
__asm_invalidate_icache_all();
|
2016-10-19 21:18:46 +00:00
|
|
|
__asm_invalidate_l3_icache();
|
2013-12-14 03:47:35 +00:00
|
|
|
}
|
|
|
|
|
2019-05-03 13:41:00 +00:00
|
|
|
#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
|
2013-12-14 03:47:35 +00:00
|
|
|
|
|
|
|
void icache_enable(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void icache_disable(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
int icache_status(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void invalidate_icache_all(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2019-05-03 13:41:00 +00:00
|
|
|
#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
|
2013-12-14 03:47:35 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable dCache & iCache, whether cache is actually enabled
|
|
|
|
* depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
|
|
|
|
*/
|
2014-06-23 22:15:54 +00:00
|
|
|
void __weak enable_caches(void)
|
2013-12-14 03:47:35 +00:00
|
|
|
{
|
|
|
|
icache_enable();
|
|
|
|
dcache_enable();
|
|
|
|
}
|