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57 lines
1.9 KiB
C
57 lines
1.9 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause */
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/**********************************************************************
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* Copyright (C) 2012-2018 Cadence Design Systems, Inc.
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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**********************************************************************
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* Cadence Core Driver for LPDDR4.
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**********************************************************************
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*/
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#ifndef LPDDR4_PRIV_H
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#define LPDDR4_PRIV_H
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#define PRODUCT_ID (0x1046U)
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#define VERSION_0 (0x54d5da40U)
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#define VERSION_1 (0xc1865a1U)
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#define BIT_MASK (0x1U)
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#define BYTE_MASK (0xffU)
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#define NIBBLE_MASK (0xfU)
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#define WORD_SHIFT (32U)
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#define WORD_MASK (0xffffffffU)
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#define SLICE_WIDTH (0x100)
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/* Number of Data slices */
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#define DSLICE_NUM (4U)
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/*Number of Address Slices */
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#define ASLICE_NUM (1U)
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/* Number of accessible registers in each slice */
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#define DSLICE0_REG_COUNT (140U)
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#define DSLICE1_REG_COUNT (140U)
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#define DSLICE2_REG_COUNT (140U)
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#define DSLICE3_REG_COUNT (140U)
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#define ASLICE0_REG_COUNT (52U)
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#define PHY_CORE_REG_COUNT (140U)
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#define CTL_OFFSET 0
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#define PI_OFFSET (((uint32_t)1) << 11)
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#define PHY_OFFSET (((uint32_t)1) << 12)
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/* BIT[17] on INT_MASK_1 register. */
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#define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT)
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/* Init Error information bits */
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#define PLL_READY (0x3U)
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#define IO_CALIB_DONE ((uint32_t)0x1U << 23U)
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#define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U)
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#define IO_CALIB_STATE ((uint32_t)0xBU << 28U)
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#define RX_CAL_DONE ((uint32_t)BIT_MASK << 4U)
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#define CA_TRAIN_RL (((uint32_t)BIT_MASK << 5U) | ((uint32_t)BIT_MASK << 4U))
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#define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U)
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#define GATE_LVL_ERROR_FIELDS (((uint32_t)BIT_MASK << 7U) | ((uint32_t)BIT_MASK << 6U))
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#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | (((uint32_t)BYTE_MASK) << 16U))
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#define DQ_LVL_STATUS (((uint32_t)BIT_MASK << 26U) | (((uint32_t)BYTE_MASK) << 18U))
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#endif /* LPDDR4_PRIV_H */
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