2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2011-11-08 23:18:08 +00:00
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/*
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* Freescale i.MX28 BCH Register Definitions
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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2020-05-04 14:08:53 +00:00
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* Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved.
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2020-05-04 14:09:00 +00:00
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* Copyright 2020 NXP
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2020-05-04 14:08:53 +00:00
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*
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2011-11-08 23:18:08 +00:00
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*/
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#ifndef __MX28_REGS_BCH_H__
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#define __MX28_REGS_BCH_H__
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2017-06-29 08:16:06 +00:00
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#include <asm/mach-imx/regs-common.h>
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2011-11-08 23:18:08 +00:00
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#ifndef __ASSEMBLY__
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2012-08-05 09:05:31 +00:00
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struct mxs_bch_regs {
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2012-08-05 09:05:30 +00:00
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mxs_reg_32(hw_bch_ctrl)
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mxs_reg_32(hw_bch_status0)
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mxs_reg_32(hw_bch_mode)
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mxs_reg_32(hw_bch_encodeptr)
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mxs_reg_32(hw_bch_dataptr)
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mxs_reg_32(hw_bch_metaptr)
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2011-11-08 23:18:08 +00:00
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uint32_t reserved[4];
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2012-08-05 09:05:30 +00:00
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mxs_reg_32(hw_bch_layoutselect)
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mxs_reg_32(hw_bch_flash0layout0)
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mxs_reg_32(hw_bch_flash0layout1)
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mxs_reg_32(hw_bch_flash1layout0)
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mxs_reg_32(hw_bch_flash1layout1)
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mxs_reg_32(hw_bch_flash2layout0)
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mxs_reg_32(hw_bch_flash2layout1)
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mxs_reg_32(hw_bch_flash3layout0)
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mxs_reg_32(hw_bch_flash3layout1)
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mxs_reg_32(hw_bch_dbgkesread)
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mxs_reg_32(hw_bch_dbgcsferead)
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mxs_reg_32(hw_bch_dbgsyndegread)
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mxs_reg_32(hw_bch_dbgahbmread)
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mxs_reg_32(hw_bch_blockname)
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mxs_reg_32(hw_bch_version)
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2020-05-04 14:08:53 +00:00
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mxs_reg_32(hw_bch_debug1)
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2011-11-08 23:18:08 +00:00
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};
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#endif
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#define BCH_CTRL_SFTRST (1 << 31)
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#define BCH_CTRL_CLKGATE (1 << 30)
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#define BCH_CTRL_DEBUGSYNDROME (1 << 22)
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#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18)
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#define BCH_CTRL_M2M_LAYOUT_OFFSET 18
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#define BCH_CTRL_M2M_ENCODE (1 << 17)
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#define BCH_CTRL_M2M_ENABLE (1 << 16)
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#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10)
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#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
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#define BCH_CTRL_BM_ERROR_IRQ (1 << 3)
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#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2)
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#define BCH_CTRL_COMPLETE_IRQ (1 << 0)
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#define BCH_STATUS0_HANDLE_MASK (0xfff << 20)
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#define BCH_STATUS0_HANDLE_OFFSET 20
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#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16)
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#define BCH_STATUS0_COMPLETED_CE_OFFSET 16
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#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8)
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#define BCH_STATUS0_STATUS_BLK0_OFFSET 8
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#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8)
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#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8)
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#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8)
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#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8)
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#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8)
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#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8)
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#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8)
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#define BCH_STATUS0_ALLONES (1 << 4)
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#define BCH_STATUS0_CORRECTED (1 << 3)
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#define BCH_STATUS0_UNCORRECTABLE (1 << 2)
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#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff
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#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
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2020-05-04 14:08:53 +00:00
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#define BCH_MODE_ERASE_THRESHOLD(v) \
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(((v) << BCH_MODE_ERASE_THRESHOLD_OFFSET) & \
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BCH_MODE_ERASE_THRESHOLD_MASK)
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2011-11-08 23:18:08 +00:00
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#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff
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#define BCH_ENCODEPTR_ADDR_OFFSET 0
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#define BCH_DATAPTR_ADDR_MASK 0xffffffff
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#define BCH_DATAPTR_ADDR_OFFSET 0
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#define BCH_METAPTR_ADDR_MASK 0xffffffff
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#define BCH_METAPTR_ADDR_OFFSET 0
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#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30)
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#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30
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#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28)
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#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28
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#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26)
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#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26
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#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24)
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#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24
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#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22)
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#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22
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#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20)
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#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20
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#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18)
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#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18
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#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16)
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#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16
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#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14)
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#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14
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#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12)
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#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12
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#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10)
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#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10
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#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8)
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#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8
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#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6)
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#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6
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#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4)
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#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4
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#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2)
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#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2
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#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0)
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#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0
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#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24)
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#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
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#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
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#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
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2020-05-04 14:09:00 +00:00
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
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2013-04-15 21:14:12 +00:00
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#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
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#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
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#else
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2011-11-08 23:18:08 +00:00
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#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
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#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
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2013-04-15 21:14:12 +00:00
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#endif
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2011-11-08 23:18:08 +00:00
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#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12)
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#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
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2020-05-04 14:08:58 +00:00
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#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_MASK BIT(10)
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2015-07-21 08:15:19 +00:00
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#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10
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2020-05-04 14:08:58 +00:00
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#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0x3ff
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2011-11-08 23:18:08 +00:00
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#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
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#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
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#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
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2020-05-04 14:09:00 +00:00
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
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2013-04-15 21:14:12 +00:00
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#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
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#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
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#else
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2011-11-08 23:18:08 +00:00
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#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
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#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
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2013-04-15 21:14:12 +00:00
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#endif
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2011-11-08 23:18:08 +00:00
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#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12)
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#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
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2020-05-04 14:08:58 +00:00
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#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_MASK BIT(10)
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2015-07-21 08:15:19 +00:00
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#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10
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2020-05-04 14:08:58 +00:00
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#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0x3ff
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2011-11-08 23:18:08 +00:00
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#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
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#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27)
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#define BCH_DEBUG0_RSVD1_OFFSET 27
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#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26)
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#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25)
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#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16)
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#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16
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#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16)
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#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16)
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#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15)
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#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14)
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#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13)
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#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12)
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#define BCH_DEBUG0_KES_STANDALONE (1 << 11)
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#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10)
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#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9)
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#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8)
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#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6)
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#define BCH_DEBUG0_RSVD0_OFFSET 6
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#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f
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#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0
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#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff
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#define BCH_DBGKESREAD_VALUES_OFFSET 0
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#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff
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#define BCH_DBGCSFEREAD_VALUES_OFFSET 0
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#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff
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#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0
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#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff
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#define BCH_DBGAHBMREAD_VALUES_OFFSET 0
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#define BCH_BLOCKNAME_NAME_MASK 0xffffffff
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#define BCH_BLOCKNAME_NAME_OFFSET 0
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#define BCH_VERSION_MAJOR_MASK (0xff << 24)
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#define BCH_VERSION_MAJOR_OFFSET 24
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#define BCH_VERSION_MINOR_MASK (0xff << 16)
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#define BCH_VERSION_MINOR_OFFSET 16
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#define BCH_VERSION_STEP_MASK 0xffff
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#define BCH_VERSION_STEP_OFFSET 0
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#endif /* __MX28_REGS_BCH_H__ */
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