2020-04-19 13:58:30 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Actions Semi S700 Register Definitions
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*
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*/
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#ifndef _OWL_REGS_S700_H_
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#define _OWL_REGS_S700_H_
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#define CMU_COREPLL 0x0000
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#define CMU_DEVPLL 0x0004
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#define CMU_DDRPLL 0x0008
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#define CMU_NANDPLL 0x000C
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#define CMU_DISPLAYPLL 0x0010
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#define CMU_AUDIOPLL 0x0014
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#define CMU_TVOUTPLL 0x0018
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#define CMU_BUSCLK 0x001C
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#define CMU_SENSORCLK 0x0020
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#define CMU_LCDCLK 0x0024
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#define CMU_DSIPLLCLK 0x0028
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#define CMU_CSICLK 0x002C
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#define CMU_DECLK 0x0030
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#define CMU_SICLK 0x0034
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#define CMU_BUSCLK1 0x0038
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#define CMU_HDECLK 0x003C
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#define CMU_VDECLK 0x0040
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#define CMU_VCECLK 0x0044
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#define CMU_NANDCCLK 0x004C
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#define CMU_SD0CLK 0x0050
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#define CMU_SD1CLK 0x0054
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#define CMU_SD2CLK 0x0058
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#define CMU_UART0CLK 0x005C
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#define CMU_UART1CLK 0x0060
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#define CMU_UART2CLK 0x0064
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#define CMU_UART3CLK 0x0068
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#define CMU_UART4CLK 0x006C
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#define CMU_UART5CLK 0x0070
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#define CMU_UART6CLK 0x0074
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#define CMU_PWM0CLK 0x0078
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#define CMU_PWM1CLK 0x007C
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#define CMU_PWM2CLK 0x0080
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#define CMU_PWM3CLK 0x0084
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#define CMU_PWM4CLK 0x0088
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#define CMU_PWM5CLK 0x008C
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#define CMU_GPU3DCLK 0x0090
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#define CMU_CORECTL 0x009C
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#define CMU_DEVCLKEN0 0x00A0
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#define CMU_DEVCLKEN1 0x00A4
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#define CMU_DEVRST0 0x00A8
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#define CMU_DEVRST1 0x00AC
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#define CMU_USBPLL 0x00B0
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#define CMU_ETHERNETPLL 0x00B4
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#define CMU_CVBSPLL 0x00B8
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#define CMU_SSTSCLK 0x00C0
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2020-05-09 14:25:09 +00:00
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#define CMU_DEVCLKEN1_ETH BIT(23)
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2020-05-09 14:25:12 +00:00
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#define GPIO_MFP_PWM (0xE01B0000)
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#define MFP_CTL0 (GPIO_MFP_PWM + 0x40)
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#define MFP_CTL1 (GPIO_MFP_PWM + 0x44)
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#define MFP_CTL2 (GPIO_MFP_PWM + 0x48)
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#define MFP_CTL3 (GPIO_MFP_PWM + 0x4C)
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2020-04-19 13:58:30 +00:00
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#endif
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